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HT32_STD_Documents 1.0.0
For HT32F52352
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Type definitions for the System Control Block Registers. More...
Modules | |
| System Controls not in SCB (SCnSCB) | |
| Type definitions for the System Control and ID Register not in the SCB. | |
| Implementation Control Block register (ICB) | |
| Type definitions for the Implementation Control Block Register. | |
Classes | |
| struct | SCB_Type |
| Structure type to access the System Control Block (SCB). More... | |
| struct | EMSS_Type |
Type definitions for the System Control Block Registers.
| #define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) |
| #define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) |
| #define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) |
| #define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U |
| #define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U |
| #define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U |
| #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) |
| #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) |
| #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) |
| #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) |
| #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) |
| #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) |
| #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) |
| #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) |
| #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U |
| #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U |
| #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U |
| #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U |
| #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U |
| #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U |
| #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U |
| #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U |
| #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) |
| #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) |
| #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) |
| #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) |
| #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) |
| #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) |
| #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) |
| #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) |
| #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U |
| #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U |
| #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U |
| #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U |
| #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U |
| #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U |
| #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U |
| #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U |
| #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) |
| #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) |
| #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) |
| #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) |
| #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) |
| #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) |
| #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) |
| #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) |
| #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U |
| #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U |
| #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U |
| #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U |
| #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U |
| #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U |
| #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U |
| #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U |
| #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) |
| #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) |
| #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) |
| #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) |
| #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) |
| #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) |
| #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) |
| #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) |
| #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U |
| #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U |
| #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U |
| #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U |
| #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U |
| #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U |
| #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U |
| #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U |
| #define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) |
| #define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) |
| #define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) |
| #define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U |
| #define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U |
| #define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U |
| #define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) |
| #define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) |
| #define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) |
| #define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U |
| #define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U |
| #define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U |
| #define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) |
| #define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) |
| #define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) |
| #define CoreDebug_DHCSR_C_PMOV_Pos 6U |
| #define CoreDebug_DHCSR_C_PMOV_Pos 6U |
| #define CoreDebug_DHCSR_C_PMOV_Pos 6U |
| #define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) |
| #define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) |
| #define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) |
| #define CoreDebug_DHCSR_S_FPD_Pos 23U |
| #define CoreDebug_DHCSR_S_FPD_Pos 23U |
| #define CoreDebug_DHCSR_S_FPD_Pos 23U |
| #define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) |
| #define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) |
| #define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) |
| #define CoreDebug_DHCSR_S_NSUIDE_Pos 21U |
| #define CoreDebug_DHCSR_S_NSUIDE_Pos 21U |
| #define CoreDebug_DHCSR_S_NSUIDE_Pos 21U |
| #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) |
| #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) |
| #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) |
| #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) |
| #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) |
| #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) |
| #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) |
| #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) |
| #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U |
| #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U |
| #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U |
| #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U |
| #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U |
| #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U |
| #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U |
| #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U |
| #define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) |
| #define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) |
| #define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) |
| #define CoreDebug_DHCSR_S_SDE_Pos 20U |
| #define CoreDebug_DHCSR_S_SDE_Pos 20U |
| #define CoreDebug_DHCSR_S_SDE_Pos 20U |
| #define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) |
| #define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) |
| #define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) |
| #define CoreDebug_DHCSR_S_SUIDE_Pos 22U |
| #define CoreDebug_DHCSR_S_SUIDE_Pos 22U |
| #define CoreDebug_DHCSR_S_SUIDE_Pos 22U |
| #define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) |
| #define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) |
| #define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) |
| #define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U |
| #define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U |
| #define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U |
| #define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) |
| #define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) |
| #define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) |
| #define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U |
| #define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U |
| #define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U |
| #define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) |
| #define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) |
| #define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) |
| #define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U |
| #define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U |
| #define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U |
| #define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) |
| #define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) |
| #define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) |
| #define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U |
| #define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U |
| #define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U |
| #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) |
| #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) |
| #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) |
| #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) |
| #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) |
| #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) |
| #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) |
| #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) |
| #define CoreDebug_DSCSR_CDS_Pos 16U |
| #define CoreDebug_DSCSR_CDS_Pos 16U |
| #define CoreDebug_DSCSR_CDS_Pos 16U |
| #define CoreDebug_DSCSR_CDS_Pos 16U |
| #define CoreDebug_DSCSR_CDS_Pos 16U |
| #define CoreDebug_DSCSR_CDS_Pos 16U |
| #define CoreDebug_DSCSR_CDS_Pos 16U |
| #define CoreDebug_DSCSR_CDS_Pos 16U |
| #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) |
| #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) |
| #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) |
| #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) |
| #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) |
| #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) |
| #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) |
| #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) |
| #define CoreDebug_DSCSR_SBRSEL_Pos 1U |
| #define CoreDebug_DSCSR_SBRSEL_Pos 1U |
| #define CoreDebug_DSCSR_SBRSEL_Pos 1U |
| #define CoreDebug_DSCSR_SBRSEL_Pos 1U |
| #define CoreDebug_DSCSR_SBRSEL_Pos 1U |
| #define CoreDebug_DSCSR_SBRSEL_Pos 1U |
| #define CoreDebug_DSCSR_SBRSEL_Pos 1U |
| #define CoreDebug_DSCSR_SBRSEL_Pos 1U |
| #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) |
| #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) |
| #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) |
| #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) |
| #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) |
| #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) |
| #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) |
| #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) |
| #define CoreDebug_DSCSR_SBRSELEN_Pos 0U |
| #define CoreDebug_DSCSR_SBRSELEN_Pos 0U |
| #define CoreDebug_DSCSR_SBRSELEN_Pos 0U |
| #define CoreDebug_DSCSR_SBRSELEN_Pos 0U |
| #define CoreDebug_DSCSR_SBRSELEN_Pos 0U |
| #define CoreDebug_DSCSR_SBRSELEN_Pos 0U |
| #define CoreDebug_DSCSR_SBRSELEN_Pos 0U |
| #define CoreDebug_DSCSR_SBRSELEN_Pos 0U |
| #define DCB_BASE (0xE000EDF0UL) |
DCB Base Address
| #define DCB_BASE (0xE000EDF0UL) |
DCB Base Address
| #define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) |
DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask
| #define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) |
DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask
| #define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) |
DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask
| #define DCB_DAUTHCTRL_FSDMA_Pos 8U |
DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position
| #define DCB_DAUTHCTRL_FSDMA_Pos 8U |
DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position
| #define DCB_DAUTHCTRL_FSDMA_Pos 8U |
DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position
| #define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) |
DCB DAUTHCTRL: Internal Secure invasive debug enable Mask
| #define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) |
DCB DAUTHCTRL: Internal Secure invasive debug enable Mask
| #define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U |
DCB DAUTHCTRL: Internal Secure invasive debug enable Position
| #define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U |
DCB DAUTHCTRL: Internal Secure invasive debug enable Position
| #define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) |
DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask
| #define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) |
DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask
| #define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U |
DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position
| #define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U |
DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position
| #define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) |
DCB DAUTHCTRL: Secure invasive debug enable select Mask
| #define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) |
DCB DAUTHCTRL: Secure invasive debug enable select Mask
| #define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U |
DCB DAUTHCTRL: Secure invasive debug enable select Position
| #define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U |
DCB DAUTHCTRL: Secure invasive debug enable select Position
| #define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) |
DCB DAUTHCTRL: Secure non-invasive debug enable select Mask
| #define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) |
DCB DAUTHCTRL: Secure non-invasive debug enable select Mask
| #define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U |
DCB DAUTHCTRL: Secure non-invasive debug enable select Position
| #define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U |
DCB DAUTHCTRL: Secure non-invasive debug enable select Position
| #define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) |
DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask
| #define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) |
DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask
| #define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) |
DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask
| #define DCB_DAUTHCTRL_UIDAPEN_Pos 9U |
DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position
| #define DCB_DAUTHCTRL_UIDAPEN_Pos 9U |
DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position
| #define DCB_DAUTHCTRL_UIDAPEN_Pos 9U |
DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position
| #define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) |
DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask
| #define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) |
DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask
| #define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) |
DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask
| #define DCB_DAUTHCTRL_UIDEN_Pos 10U |
DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position
| #define DCB_DAUTHCTRL_UIDEN_Pos 10U |
DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position
| #define DCB_DAUTHCTRL_UIDEN_Pos 10U |
DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position
| #define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) |
DCB DCRDR: Data temporary buffer Mask
| #define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) |
DCB DCRDR: Data temporary buffer Mask
| #define DCB_DCRDR_DBGTMP_Pos 0U |
DCB DCRDR: Data temporary buffer Position
| #define DCB_DCRDR_DBGTMP_Pos 0U |
DCB DCRDR: Data temporary buffer Position
| #define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) |
DCB DCRSR: Register selector Mask
| #define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) |
DCB DCRSR: Register selector Mask
| #define DCB_DCRSR_REGSEL_Pos 0U |
DCB DCRSR: Register selector Position
| #define DCB_DCRSR_REGSEL_Pos 0U |
DCB DCRSR: Register selector Position
| #define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) |
DCB DCRSR: Register write/not-read Mask
| #define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) |
DCB DCRSR: Register write/not-read Mask
| #define DCB_DCRSR_REGWnR_Pos 16U |
DCB DCRSR: Register write/not-read Position
| #define DCB_DCRSR_REGWnR_Pos 16U |
DCB DCRSR: Register write/not-read Position
| #define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) |
DCB DEMCR: Trace enable Mask
| #define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) |
DCB DEMCR: Trace enable Mask
| #define DCB_DEMCR_TRCENA_Pos 24U |
DCB DEMCR: Trace enable Position
| #define DCB_DEMCR_TRCENA_Pos 24U |
DCB DEMCR: Trace enable Position
| #define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) |
DCB DEMCR: Vector Catch Core reset Mask
| #define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) |
DCB DEMCR: Vector Catch Core reset Mask
| #define DCB_DEMCR_VC_CORERESET_Pos 0U |
DCB DEMCR: Vector Catch Core reset Position
| #define DCB_DEMCR_VC_CORERESET_Pos 0U |
DCB DEMCR: Vector Catch Core reset Position
| #define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) |
DCB DEMCR: Vector Catch HardFault errors Mask
| #define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) |
DCB DEMCR: Vector Catch HardFault errors Mask
| #define DCB_DEMCR_VC_HARDERR_Pos 10U |
DCB DEMCR: Vector Catch HardFault errors Position
| #define DCB_DEMCR_VC_HARDERR_Pos 10U |
DCB DEMCR: Vector Catch HardFault errors Position
| #define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) |
DCB DHCSR: Debug enable control Mask
| #define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) |
DCB DHCSR: Debug enable control Mask
| #define DCB_DHCSR_C_DEBUGEN_Pos 0U |
DCB DHCSR: Debug enable control Position
| #define DCB_DHCSR_C_DEBUGEN_Pos 0U |
DCB DHCSR: Debug enable control Position
| #define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) |
DCB DHCSR: Halt control Mask
| #define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) |
DCB DHCSR: Halt control Mask
| #define DCB_DHCSR_C_HALT_Pos 1U |
DCB DHCSR: Halt control Position
| #define DCB_DHCSR_C_HALT_Pos 1U |
DCB DHCSR: Halt control Position
| #define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) |
DCB DHCSR: Mask interrupts control Mask
| #define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) |
DCB DHCSR: Mask interrupts control Mask
| #define DCB_DHCSR_C_MASKINTS_Pos 3U |
DCB DHCSR: Mask interrupts control Position
| #define DCB_DHCSR_C_MASKINTS_Pos 3U |
DCB DHCSR: Mask interrupts control Position
| #define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) |
DCB DHCSR: Halt on PMU overflow control Mask
| #define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) |
DCB DHCSR: Halt on PMU overflow control Mask
| #define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) |
DCB DHCSR: Halt on PMU overflow control Mask
| #define DCB_DHCSR_C_PMOV_Pos 6U |
DCB DHCSR: Halt on PMU overflow control Position
| #define DCB_DHCSR_C_PMOV_Pos 6U |
DCB DHCSR: Halt on PMU overflow control Position
| #define DCB_DHCSR_C_PMOV_Pos 6U |
DCB DHCSR: Halt on PMU overflow control Position
| #define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) |
DCB DHCSR: Step control Mask
| #define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) |
DCB DHCSR: Step control Mask
| #define DCB_DHCSR_C_STEP_Pos 2U |
DCB DHCSR: Step control Position
| #define DCB_DHCSR_C_STEP_Pos 2U |
DCB DHCSR: Step control Position
| #define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) |
DCB DHCSR: Debug key Mask
| #define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) |
DCB DHCSR: Debug key Mask
| #define DCB_DHCSR_DBGKEY_Pos 16U |
DCB DHCSR: Debug key Position
| #define DCB_DHCSR_DBGKEY_Pos 16U |
DCB DHCSR: Debug key Position
| #define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) |
DCB DHCSR: Floating-point registers Debuggable Mask
| #define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) |
DCB DHCSR: Floating-point registers Debuggable Mask
| #define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) |
DCB DHCSR: Floating-point registers Debuggable Mask
| #define DCB_DHCSR_S_FPD_Pos 23U |
DCB DHCSR: Floating-point registers Debuggable Position
| #define DCB_DHCSR_S_FPD_Pos 23U |
DCB DHCSR: Floating-point registers Debuggable Position
| #define DCB_DHCSR_S_FPD_Pos 23U |
DCB DHCSR: Floating-point registers Debuggable Position
| #define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) |
DCB DHCSR: Halted status Mask
| #define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) |
DCB DHCSR: Halted status Mask
| #define DCB_DHCSR_S_HALT_Pos 17U |
DCB DHCSR: Halted status Position
| #define DCB_DHCSR_S_HALT_Pos 17U |
DCB DHCSR: Halted status Position
| #define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) |
DCB DHCSR: Lockup status Mask
| #define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) |
DCB DHCSR: Lockup status Mask
| #define DCB_DHCSR_S_LOCKUP_Pos 19U |
DCB DHCSR: Lockup status Position
| #define DCB_DHCSR_S_LOCKUP_Pos 19U |
DCB DHCSR: Lockup status Position
| #define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) |
DCB DHCSR: Non-secure unprivileged halting debug enabled Mask
| #define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) |
DCB DHCSR: Non-secure unprivileged halting debug enabled Mask
| #define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) |
DCB DHCSR: Non-secure unprivileged halting debug enabled Mask
| #define DCB_DHCSR_S_NSUIDE_Pos 21U |
DCB DHCSR: Non-secure unprivileged halting debug enabled Position
| #define DCB_DHCSR_S_NSUIDE_Pos 21U |
DCB DHCSR: Non-secure unprivileged halting debug enabled Position
| #define DCB_DHCSR_S_NSUIDE_Pos 21U |
DCB DHCSR: Non-secure unprivileged halting debug enabled Position
| #define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) |
DCB DHCSR: Register ready status Mask
| #define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) |
DCB DHCSR: Register ready status Mask
| #define DCB_DHCSR_S_REGRDY_Pos 16U |
DCB DHCSR: Register ready status Position
| #define DCB_DHCSR_S_REGRDY_Pos 16U |
DCB DHCSR: Register ready status Position
| #define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) |
DCB DHCSR: Reset sticky status Mask
| #define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) |
DCB DHCSR: Reset sticky status Mask
| #define DCB_DHCSR_S_RESET_ST_Pos 25U |
DCB DHCSR: Reset sticky status Position
| #define DCB_DHCSR_S_RESET_ST_Pos 25U |
DCB DHCSR: Reset sticky status Position
| #define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) |
DCB DHCSR: Restart sticky status Mask
| #define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) |
DCB DHCSR: Restart sticky status Mask
| #define DCB_DHCSR_S_RESTART_ST_Pos 26U |
DCB DHCSR: Restart sticky status Position
| #define DCB_DHCSR_S_RESTART_ST_Pos 26U |
DCB DHCSR: Restart sticky status Position
| #define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) |
DCB DHCSR: Retire sticky status Mask
| #define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) |
DCB DHCSR: Retire sticky status Mask
| #define DCB_DHCSR_S_RETIRE_ST_Pos 24U |
DCB DHCSR: Retire sticky status Position
| #define DCB_DHCSR_S_RETIRE_ST_Pos 24U |
DCB DHCSR: Retire sticky status Position
| #define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) |
DCB DHCSR: Secure debug enabled Mask
| #define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) |
DCB DHCSR: Secure debug enabled Mask
| #define DCB_DHCSR_S_SDE_Pos 20U |
DCB DHCSR: Secure debug enabled Position
| #define DCB_DHCSR_S_SDE_Pos 20U |
DCB DHCSR: Secure debug enabled Position
| #define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) |
DCB DHCSR: Sleeping status Mask
| #define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) |
DCB DHCSR: Sleeping status Mask
| #define DCB_DHCSR_S_SLEEP_Pos 18U |
DCB DHCSR: Sleeping status Position
| #define DCB_DHCSR_S_SLEEP_Pos 18U |
DCB DHCSR: Sleeping status Position
| #define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) |
DCB DHCSR: Secure unprivileged halting debug enabled Mask
| #define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) |
DCB DHCSR: Secure unprivileged halting debug enabled Mask
| #define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) |
DCB DHCSR: Secure unprivileged halting debug enabled Mask
| #define DCB_DHCSR_S_SUIDE_Pos 22U |
DCB DHCSR: Secure unprivileged halting debug enabled Position
| #define DCB_DHCSR_S_SUIDE_Pos 22U |
DCB DHCSR: Secure unprivileged halting debug enabled Position
| #define DCB_DHCSR_S_SUIDE_Pos 22U |
DCB DHCSR: Secure unprivileged halting debug enabled Position
| #define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) |
DCB DSCEMCR: Clear monitor pend Mask
| #define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) |
DCB DSCEMCR: Clear monitor pend Mask
| #define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) |
DCB DSCEMCR: Clear monitor pend Mask
| #define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U |
DCB DSCEMCR: Clear monitor pend Position
| #define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U |
DCB DSCEMCR: Clear monitor pend Position
| #define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U |
DCB DSCEMCR: Clear monitor pend Position
| #define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) |
DCB DSCEMCR: Clear monitor request Mask
| #define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) |
DCB DSCEMCR: Clear monitor request Mask
| #define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) |
DCB DSCEMCR: Clear monitor request Mask
| #define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U |
DCB DSCEMCR: Clear monitor request Position
| #define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U |
DCB DSCEMCR: Clear monitor request Position
| #define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U |
DCB DSCEMCR: Clear monitor request Position
| #define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) |
DCB DSCEMCR: Set monitor pend Mask
| #define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) |
DCB DSCEMCR: Set monitor pend Mask
| #define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) |
DCB DSCEMCR: Set monitor pend Mask
| #define DCB_DSCEMCR_SET_MON_PEND_Pos 1U |
DCB DSCEMCR: Set monitor pend Position
| #define DCB_DSCEMCR_SET_MON_PEND_Pos 1U |
DCB DSCEMCR: Set monitor pend Position
| #define DCB_DSCEMCR_SET_MON_PEND_Pos 1U |
DCB DSCEMCR: Set monitor pend Position
| #define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) |
DCB DSCEMCR: Set monitor request Mask
| #define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) |
DCB DSCEMCR: Set monitor request Mask
| #define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) |
DCB DSCEMCR: Set monitor request Mask
| #define DCB_DSCEMCR_SET_MON_REQ_Pos 3U |
DCB DSCEMCR: Set monitor request Position
| #define DCB_DSCEMCR_SET_MON_REQ_Pos 3U |
DCB DSCEMCR: Set monitor request Position
| #define DCB_DSCEMCR_SET_MON_REQ_Pos 3U |
DCB DSCEMCR: Set monitor request Position
| #define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) |
DCB DSCSR: Current domain Secure Mask
| #define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) |
DCB DSCSR: Current domain Secure Mask
| #define DCB_DSCSR_CDS_Pos 16U |
DCB DSCSR: Current domain Secure Position
| #define DCB_DSCSR_CDS_Pos 16U |
DCB DSCSR: Current domain Secure Position
| #define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) |
DCB DSCSR: CDS write-enable key Mask
| #define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) |
DCB DSCSR: CDS write-enable key Mask
| #define DCB_DSCSR_CDSKEY_Pos 17U |
DCB DSCSR: CDS write-enable key Position
| #define DCB_DSCSR_CDSKEY_Pos 17U |
DCB DSCSR: CDS write-enable key Position
| #define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) |
DCB DSCSR: Secure banked register select Mask
| #define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) |
DCB DSCSR: Secure banked register select Mask
| #define DCB_DSCSR_SBRSEL_Pos 1U |
DCB DSCSR: Secure banked register select Position
| #define DCB_DSCSR_SBRSEL_Pos 1U |
DCB DSCSR: Secure banked register select Position
| #define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) |
DCB DSCSR: Secure banked register select enable Mask
| #define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) |
DCB DSCSR: Secure banked register select enable Mask
| #define DCB_DSCSR_SBRSELEN_Pos 0U |
DCB DSCSR: Secure banked register select enable Position
| #define DCB_DSCSR_SBRSELEN_Pos 0U |
DCB DSCSR: Secure banked register select enable Position
| #define DIB_BASE (0xE000EFB0UL) |
DIB Base Address
| #define DIB_BASE (0xE000EFB0UL) |
DIB Base Address
| #define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) |
DIB DAUTHSTATUS: Non-secure Invasive Debug Mask
| #define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) |
DIB DAUTHSTATUS: Non-secure Invasive Debug Mask
| #define DIB_DAUTHSTATUS_NSID_Pos 0U |
DIB DAUTHSTATUS: Non-secure Invasive Debug Position
| #define DIB_DAUTHSTATUS_NSID_Pos 0U |
DIB DAUTHSTATUS: Non-secure Invasive Debug Position
| #define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) |
DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask
| #define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) |
DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask
| #define DIB_DAUTHSTATUS_NSNID_Pos 2U |
DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position
| #define DIB_DAUTHSTATUS_NSNID_Pos 2U |
DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position
| #define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) |
DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask
| #define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) |
DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask
| #define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) |
DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask
| #define DIB_DAUTHSTATUS_NSUID_Pos 16U |
DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position
| #define DIB_DAUTHSTATUS_NSUID_Pos 16U |
DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position
| #define DIB_DAUTHSTATUS_NSUID_Pos 16U |
DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position
| #define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) |
DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask
| #define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) |
DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask
| #define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) |
DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask
| #define DIB_DAUTHSTATUS_NSUNID_Pos 18U |
DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position
| #define DIB_DAUTHSTATUS_NSUNID_Pos 18U |
DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position
| #define DIB_DAUTHSTATUS_NSUNID_Pos 18U |
DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position
| #define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) |
DIB DAUTHSTATUS: Secure Invasive Debug Mask
| #define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) |
DIB DAUTHSTATUS: Secure Invasive Debug Mask
| #define DIB_DAUTHSTATUS_SID_Pos 4U |
DIB DAUTHSTATUS: Secure Invasive Debug Position
| #define DIB_DAUTHSTATUS_SID_Pos 4U |
DIB DAUTHSTATUS: Secure Invasive Debug Position
| #define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) |
DIB DAUTHSTATUS: Secure Non-invasive Debug Mask
| #define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) |
DIB DAUTHSTATUS: Secure Non-invasive Debug Mask
| #define DIB_DAUTHSTATUS_SNID_Pos 6U |
DIB DAUTHSTATUS: Secure Non-invasive Debug Position
| #define DIB_DAUTHSTATUS_SNID_Pos 6U |
DIB DAUTHSTATUS: Secure Non-invasive Debug Position
| #define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) |
DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask
| #define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) |
DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask
| #define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) |
DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask
| #define DIB_DAUTHSTATUS_SUID_Pos 20U |
DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position
| #define DIB_DAUTHSTATUS_SUID_Pos 20U |
DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position
| #define DIB_DAUTHSTATUS_SUID_Pos 20U |
DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position
| #define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) |
DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask
| #define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) |
DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask
| #define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) |
DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask
| #define DIB_DAUTHSTATUS_SUNID_Pos 22U |
DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position
| #define DIB_DAUTHSTATUS_SUNID_Pos 22U |
DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position
| #define DIB_DAUTHSTATUS_SUNID_Pos 22U |
DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position
| #define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) |
DIB DDEVARCH: Architect Mask
| #define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) |
DIB DDEVARCH: Architect Mask
| #define DIB_DDEVARCH_ARCHITECT_Pos 21U |
DIB DDEVARCH: Architect Position
| #define DIB_DDEVARCH_ARCHITECT_Pos 21U |
DIB DDEVARCH: Architect Position
| #define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) |
DIB DDEVARCH: Architecture Part Mask
| #define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) |
DIB DDEVARCH: Architecture Part Mask
| #define DIB_DDEVARCH_ARCHPART_Pos 0U |
DIB DDEVARCH: Architecture Part Position
| #define DIB_DDEVARCH_ARCHPART_Pos 0U |
DIB DDEVARCH: Architecture Part Position
| #define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) |
DIB DDEVARCH: Architecture Version Mask
| #define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) |
DIB DDEVARCH: Architecture Version Mask
| #define DIB_DDEVARCH_ARCHVER_Pos 12U |
DIB DDEVARCH: Architecture Version Position
| #define DIB_DDEVARCH_ARCHVER_Pos 12U |
DIB DDEVARCH: Architecture Version Position
| #define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) |
DIB DDEVARCH: DEVARCH Present Mask
| #define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) |
DIB DDEVARCH: DEVARCH Present Mask
| #define DIB_DDEVARCH_PRESENT_Pos 20U |
DIB DDEVARCH: DEVARCH Present Position
| #define DIB_DDEVARCH_PRESENT_Pos 20U |
DIB DDEVARCH: DEVARCH Present Position
| #define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) |
DIB DDEVARCH: Revision Mask
| #define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) |
DIB DDEVARCH: Revision Mask
| #define DIB_DDEVARCH_REVISION_Pos 16U |
DIB DDEVARCH: Revision Position
| #define DIB_DDEVARCH_REVISION_Pos 16U |
DIB DDEVARCH: Revision Position
| #define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) |
DIB DDEVTYPE: Major type Mask
| #define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) |
DIB DDEVTYPE: Major type Mask
| #define DIB_DDEVTYPE_MAJOR_Pos 0U |
DIB DDEVTYPE: Major type Position
| #define DIB_DDEVTYPE_MAJOR_Pos 0U |
DIB DDEVTYPE: Major type Position
| #define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) |
DIB DDEVTYPE: Sub-type Mask
| #define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) |
DIB DDEVTYPE: Sub-type Mask
| #define DIB_DDEVTYPE_SUB_Pos 4U |
DIB DDEVTYPE: Sub-type Position
| #define DIB_DDEVTYPE_SUB_Pos 4U |
DIB DDEVTYPE: Sub-type Position
| #define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) |
DIB DLAR: KEY Mask
| #define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) |
DIB DLAR: KEY Mask
| #define DIB_DLAR_KEY_Pos 0U |
DIB DLAR: KEY Position
| #define DIB_DLAR_KEY_Pos 0U |
DIB DLAR: KEY Position
| #define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) |
DIB DLSR: Not thirty-two bit Mask
| #define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) |
DIB DLSR: Not thirty-two bit Mask
| #define DIB_DLSR_nTT_Pos 2U |
DIB DLSR: Not thirty-two bit Position
| #define DIB_DLSR_nTT_Pos 2U |
DIB DLSR: Not thirty-two bit Position
| #define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) |
DIB DLSR: Software Lock implemented Mask
| #define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) |
DIB DLSR: Software Lock implemented Mask
| #define DIB_DLSR_SLI_Pos 0U |
DIB DLSR: Software Lock implemented Position
| #define DIB_DLSR_SLI_Pos 0U |
DIB DLSR: Software Lock implemented Position
| #define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) |
DIB DLSR: Software Lock status Mask
| #define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) |
DIB DLSR: Software Lock status Mask
| #define DIB_DLSR_SLK_Pos 1U |
DIB DLSR: Software Lock status Position
| #define DIB_DLSR_SLK_Pos 1U |
DIB DLSR: Software Lock status Position
| #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) |
DWT FUNCTION: ACTION Mask
| #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) |
DWT FUNCTION: ACTION Mask
| #define DWT_FUNCTION_ACTION_Pos 4U |
DWT FUNCTION: ACTION Position
| #define DWT_FUNCTION_ACTION_Pos 4U |
DWT FUNCTION: ACTION Position
| #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) |
DWT FUNCTION: ID Mask
| #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) |
DWT FUNCTION: ID Mask
| #define DWT_FUNCTION_ID_Pos 27U |
DWT FUNCTION: ID Position
| #define DWT_FUNCTION_ID_Pos 27U |
DWT FUNCTION: ID Position
| #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) |
DWT FUNCTION: MATCH Mask
| #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) |
DWT FUNCTION: MATCH Mask
| #define DWT_FUNCTION_MATCH_Pos 0U |
DWT FUNCTION: MATCH Position
| #define DWT_FUNCTION_MATCH_Pos 0U |
DWT FUNCTION: MATCH Position
| #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) |
Error Banking configuration struct
| #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) |
Error Banking configuration struct
| #define ERRBNK_BASE (0xE001E100UL) |
Error Banking Base Address
| #define ERRBNK_BASE (0xE001E100UL) |
Error Banking Base Address
| #define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) |
ERRBNK DEBR0: BANK Mask
| #define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) |
ERRBNK DEBR0: BANK Mask
| #define ERRBNK_DEBR0_BANK_Pos 16U |
ERRBNK DEBR0: BANK Position
| #define ERRBNK_DEBR0_BANK_Pos 16U |
ERRBNK DEBR0: BANK Position
| #define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) |
ERRBNK DEBR0: LOCATION Mask
| #define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) |
ERRBNK DEBR0: LOCATION Mask
| #define ERRBNK_DEBR0_LOCATION_Pos 2U |
ERRBNK DEBR0: LOCATION Position
| #define ERRBNK_DEBR0_LOCATION_Pos 2U |
ERRBNK DEBR0: LOCATION Position
| #define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) |
ERRBNK DEBR0: LOCKED Mask
| #define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) |
ERRBNK DEBR0: LOCKED Mask
| #define ERRBNK_DEBR0_LOCKED_Pos 1U |
ERRBNK DEBR0: LOCKED Position
| #define ERRBNK_DEBR0_LOCKED_Pos 1U |
ERRBNK DEBR0: LOCKED Position
| #define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) |
ERRBNK DEBR0: SWDEF Mask
| #define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) |
ERRBNK DEBR0: SWDEF Mask
| #define ERRBNK_DEBR0_SWDEF_Pos 30U |
ERRBNK DEBR0: SWDEF Position
| #define ERRBNK_DEBR0_SWDEF_Pos 30U |
ERRBNK DEBR0: SWDEF Position
| #define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) |
ERRBNK DEBR0: TYPE Mask
| #define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) |
ERRBNK DEBR0: TYPE Mask
| #define ERRBNK_DEBR0_TYPE_Pos 17U |
ERRBNK DEBR0: TYPE Position
| #define ERRBNK_DEBR0_TYPE_Pos 17U |
ERRBNK DEBR0: TYPE Position
| #define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) |
ERRBNK DEBR0: VALID Mask
| #define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) |
ERRBNK DEBR0: VALID Mask
| #define ERRBNK_DEBR0_VALID_Pos 0U |
ERRBNK DEBR0: VALID Position
| #define ERRBNK_DEBR0_VALID_Pos 0U |
ERRBNK DEBR0: VALID Position
| #define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) |
ERRBNK DEBR1: BANK Mask
| #define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) |
ERRBNK DEBR1: BANK Mask
| #define ERRBNK_DEBR1_BANK_Pos 16U |
ERRBNK DEBR1: BANK Position
| #define ERRBNK_DEBR1_BANK_Pos 16U |
ERRBNK DEBR1: BANK Position
| #define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) |
ERRBNK DEBR1: LOCATION Mask
| #define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) |
ERRBNK DEBR1: LOCATION Mask
| #define ERRBNK_DEBR1_LOCATION_Pos 2U |
ERRBNK DEBR1: LOCATION Position
| #define ERRBNK_DEBR1_LOCATION_Pos 2U |
ERRBNK DEBR1: LOCATION Position
| #define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) |
ERRBNK DEBR1: LOCKED Mask
| #define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) |
ERRBNK DEBR1: LOCKED Mask
| #define ERRBNK_DEBR1_LOCKED_Pos 1U |
ERRBNK DEBR1: LOCKED Position
| #define ERRBNK_DEBR1_LOCKED_Pos 1U |
ERRBNK DEBR1: LOCKED Position
| #define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) |
ERRBNK DEBR1: SWDEF Mask
| #define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) |
ERRBNK DEBR1: SWDEF Mask
| #define ERRBNK_DEBR1_SWDEF_Pos 30U |
ERRBNK DEBR1: SWDEF Position
| #define ERRBNK_DEBR1_SWDEF_Pos 30U |
ERRBNK DEBR1: SWDEF Position
| #define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) |
ERRBNK DEBR1: TYPE Mask
| #define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) |
ERRBNK DEBR1: TYPE Mask
| #define ERRBNK_DEBR1_TYPE_Pos 17U |
ERRBNK DEBR1: TYPE Position
| #define ERRBNK_DEBR1_TYPE_Pos 17U |
ERRBNK DEBR1: TYPE Position
| #define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) |
ERRBNK DEBR1: VALID Mask
| #define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) |
ERRBNK DEBR1: VALID Mask
| #define ERRBNK_DEBR1_VALID_Pos 0U |
ERRBNK DEBR1: VALID Position
| #define ERRBNK_DEBR1_VALID_Pos 0U |
ERRBNK DEBR1: VALID Position
| #define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) |
ERRBNK IEBR0: BANK Mask
| #define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) |
ERRBNK IEBR0: BANK Mask
| #define ERRBNK_IEBR0_BANK_Pos 16U |
ERRBNK IEBR0: BANK Position
| #define ERRBNK_IEBR0_BANK_Pos 16U |
ERRBNK IEBR0: BANK Position
| #define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) |
ERRBNK IEBR0: LOCATION Mask
| #define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) |
ERRBNK IEBR0: LOCATION Mask
| #define ERRBNK_IEBR0_LOCATION_Pos 2U |
ERRBNK IEBR0: LOCATION Position
| #define ERRBNK_IEBR0_LOCATION_Pos 2U |
ERRBNK IEBR0: LOCATION Position
| #define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) |
ERRBNK IEBR0: LOCKED Mask
| #define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) |
ERRBNK IEBR0: LOCKED Mask
| #define ERRBNK_IEBR0_LOCKED_Pos 1U |
ERRBNK IEBR0: LOCKED Position
| #define ERRBNK_IEBR0_LOCKED_Pos 1U |
ERRBNK IEBR0: LOCKED Position
| #define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) |
ERRBNK IEBR0: SWDEF Mask
| #define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) |
ERRBNK IEBR0: SWDEF Mask
| #define ERRBNK_IEBR0_SWDEF_Pos 30U |
ERRBNK IEBR0: SWDEF Position
| #define ERRBNK_IEBR0_SWDEF_Pos 30U |
ERRBNK IEBR0: SWDEF Position
| #define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) |
ERRBNK IEBR0: VALID Mask
| #define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) |
ERRBNK IEBR0: VALID Mask
| #define ERRBNK_IEBR0_VALID_Pos 0U |
ERRBNK IEBR0: VALID Position
| #define ERRBNK_IEBR0_VALID_Pos 0U |
ERRBNK IEBR0: VALID Position
| #define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) |
ERRBNK IEBR1: BANK Mask
| #define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) |
ERRBNK IEBR1: BANK Mask
| #define ERRBNK_IEBR1_BANK_Pos 16U |
ERRBNK IEBR1: BANK Position
| #define ERRBNK_IEBR1_BANK_Pos 16U |
ERRBNK IEBR1: BANK Position
| #define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) |
ERRBNK IEBR1: LOCATION Mask
| #define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) |
ERRBNK IEBR1: LOCATION Mask
| #define ERRBNK_IEBR1_LOCATION_Pos 2U |
ERRBNK IEBR1: LOCATION Position
| #define ERRBNK_IEBR1_LOCATION_Pos 2U |
ERRBNK IEBR1: LOCATION Position
| #define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) |
ERRBNK IEBR1: LOCKED Mask
| #define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) |
ERRBNK IEBR1: LOCKED Mask
| #define ERRBNK_IEBR1_LOCKED_Pos 1U |
ERRBNK IEBR1: LOCKED Position
| #define ERRBNK_IEBR1_LOCKED_Pos 1U |
ERRBNK IEBR1: LOCKED Position
| #define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) |
ERRBNK IEBR1: SWDEF Mask
| #define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) |
ERRBNK IEBR1: SWDEF Mask
| #define ERRBNK_IEBR1_SWDEF_Pos 30U |
ERRBNK IEBR1: SWDEF Position
| #define ERRBNK_IEBR1_SWDEF_Pos 30U |
ERRBNK IEBR1: SWDEF Position
| #define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) |
ERRBNK IEBR1: VALID Mask
| #define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) |
ERRBNK IEBR1: VALID Mask
| #define ERRBNK_IEBR1_VALID_Pos 0U |
ERRBNK IEBR1: VALID Position
| #define ERRBNK_IEBR1_VALID_Pos 0U |
ERRBNK IEBR1: VALID Position
| #define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) |
ERRBNK TEBR0: BANK Mask
| #define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) |
ERRBNK TEBR0: BANK Mask
| #define ERRBNK_TEBR0_BANK_Pos 24U |
ERRBNK TEBR0: BANK Position
| #define ERRBNK_TEBR0_BANK_Pos 24U |
ERRBNK TEBR0: BANK Position
| #define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) |
ERRBNK TEBR0: LOCATION Mask
| #define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) |
ERRBNK TEBR0: LOCATION Mask
| #define ERRBNK_TEBR0_LOCATION_Pos 2U |
ERRBNK TEBR0: LOCATION Position
| #define ERRBNK_TEBR0_LOCATION_Pos 2U |
ERRBNK TEBR0: LOCATION Position
| #define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) |
ERRBNK TEBR0: LOCKED Mask
| #define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) |
ERRBNK TEBR0: LOCKED Mask
| #define ERRBNK_TEBR0_LOCKED_Pos 1U |
ERRBNK TEBR0: LOCKED Position
| #define ERRBNK_TEBR0_LOCKED_Pos 1U |
ERRBNK TEBR0: LOCKED Position
| #define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) |
ERRBNK TEBR0: POISON Mask
| #define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) |
ERRBNK TEBR0: POISON Mask
| #define ERRBNK_TEBR0_POISON_Pos 28U |
ERRBNK TEBR0: POISON Position
| #define ERRBNK_TEBR0_POISON_Pos 28U |
ERRBNK TEBR0: POISON Position
| #define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) |
ERRBNK TEBR0: SWDEF Mask
| #define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) |
ERRBNK TEBR0: SWDEF Mask
| #define ERRBNK_TEBR0_SWDEF_Pos 30U |
ERRBNK TEBR0: SWDEF Position
| #define ERRBNK_TEBR0_SWDEF_Pos 30U |
ERRBNK TEBR0: SWDEF Position
| #define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) |
ERRBNK TEBR0: TYPE Mask
| #define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) |
ERRBNK TEBR0: TYPE Mask
| #define ERRBNK_TEBR0_TYPE_Pos 27U |
ERRBNK TEBR0: TYPE Position
| #define ERRBNK_TEBR0_TYPE_Pos 27U |
ERRBNK TEBR0: TYPE Position
| #define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) |
ERRBNK TEBR0: VALID Mask
| #define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) |
ERRBNK TEBR0: VALID Mask
| #define ERRBNK_TEBR0_VALID_Pos 0U |
ERRBNK TEBR0: VALID Position
| #define ERRBNK_TEBR0_VALID_Pos 0U |
ERRBNK TEBR0: VALID Position
| #define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) |
ERRBNK TEBR1: BANK Mask
| #define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) |
ERRBNK TEBR1: BANK Mask
| #define ERRBNK_TEBR1_BANK_Pos 24U |
ERRBNK TEBR1: BANK Position
| #define ERRBNK_TEBR1_BANK_Pos 24U |
ERRBNK TEBR1: BANK Position
| #define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) |
ERRBNK TEBR1: LOCATION Mask
| #define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) |
ERRBNK TEBR1: LOCATION Mask
| #define ERRBNK_TEBR1_LOCATION_Pos 2U |
ERRBNK TEBR1: LOCATION Position
| #define ERRBNK_TEBR1_LOCATION_Pos 2U |
ERRBNK TEBR1: LOCATION Position
| #define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) |
ERRBNK TEBR1: LOCKED Mask
| #define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) |
ERRBNK TEBR1: LOCKED Mask
| #define ERRBNK_TEBR1_LOCKED_Pos 1U |
ERRBNK TEBR1: LOCKED Position
| #define ERRBNK_TEBR1_LOCKED_Pos 1U |
ERRBNK TEBR1: LOCKED Position
| #define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) |
ERRBNK TEBR1: POISON Mask
| #define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) |
ERRBNK TEBR1: POISON Mask
| #define ERRBNK_TEBR1_POISON_Pos 28U |
ERRBNK TEBR1: POISON Position
| #define ERRBNK_TEBR1_POISON_Pos 28U |
ERRBNK TEBR1: POISON Position
| #define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) |
ERRBNK TEBR1: SWDEF Mask
| #define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) |
ERRBNK TEBR1: SWDEF Mask
| #define ERRBNK_TEBR1_SWDEF_Pos 30U |
ERRBNK TEBR1: SWDEF Position
| #define ERRBNK_TEBR1_SWDEF_Pos 30U |
ERRBNK TEBR1: SWDEF Position
| #define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) |
ERRBNK TEBR1: TYPE Mask
| #define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) |
ERRBNK TEBR1: TYPE Mask
| #define ERRBNK_TEBR1_TYPE_Pos 27U |
ERRBNK TEBR1: TYPE Position
| #define ERRBNK_TEBR1_TYPE_Pos 27U |
ERRBNK TEBR1: TYPE Position
| #define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) |
ERRBNK TEBR1: VALID Mask
| #define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) |
ERRBNK TEBR1: VALID Mask
| #define ERRBNK_TEBR1_VALID_Pos 0U |
ERRBNK TEBR1: VALID Position
| #define ERRBNK_TEBR1_VALID_Pos 0U |
ERRBNK TEBR1: VALID Position
| #define EWIC_BASE (0xE001E400UL) |
External Wakeup Interrupt Controller Base Address
| #define EWIC_BASE (0xE001E400UL) |
External Wakeup Interrupt Controller Base Address
| #define EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/) |
EWIC EVENTMASKA: IRQ Mask
| #define EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/) |
EWIC EVENTMASKA: IRQ Mask
| #define EWIC_EVENTMASK_IRQ_Pos 0U |
EWIC EVENTMASKA: IRQ Position
| #define EWIC_EVENTMASK_IRQ_Pos 0U |
EWIC EVENTMASKA: IRQ Position
| #define EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos) |
EWIC EVENTMASKA: EDBGREQ Mask
| #define EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos) |
EWIC EVENTMASKA: EDBGREQ Mask
| #define EWIC_EVENTMASKA_EDBGREQ_Pos 2U |
EWIC EVENTMASKA: EDBGREQ Position
| #define EWIC_EVENTMASKA_EDBGREQ_Pos 2U |
EWIC EVENTMASKA: EDBGREQ Position
| #define EWIC_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/) |
EWIC EVENTMASKA: EVENT Mask
| #define EWIC_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/) |
EWIC EVENTMASKA: EVENT Mask
| #define EWIC_EVENTMASKA_EVENT_Pos 0U |
EWIC EVENTMASKA: EVENT Position
| #define EWIC_EVENTMASKA_EVENT_Pos 0U |
EWIC EVENTMASKA: EVENT Position
| #define EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos) |
EWIC EVENTMASKA: NMI Mask
| #define EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos) |
EWIC EVENTMASKA: NMI Mask
| #define EWIC_EVENTMASKA_NMI_Pos 1U |
EWIC EVENTMASKA: NMI Position
| #define EWIC_EVENTMASKA_NMI_Pos 1U |
EWIC EVENTMASKA: NMI Position
| #define EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos) |
EWIC EVENTSPR: EDBGREQ Mask
| #define EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos) |
EWIC EVENTSPR: EDBGREQ Mask
| #define EWIC_EVENTSPR_EDBGREQ_Pos 2U |
EWIC EVENTSPR: EDBGREQ Position
| #define EWIC_EVENTSPR_EDBGREQ_Pos 2U |
EWIC EVENTSPR: EDBGREQ Position
| #define EWIC_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/) |
EWIC EVENTSPR: EVENT Mask
| #define EWIC_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/) |
EWIC EVENTSPR: EVENT Mask
| #define EWIC_EVENTSPR_EVENT_Pos 0U |
EWIC EVENTSPR: EVENT Position
| #define EWIC_EVENTSPR_EVENT_Pos 0U |
EWIC EVENTSPR: EVENT Position
| #define EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos) |
EWIC EVENTSPR: NMI Mask
| #define EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos) |
EWIC EVENTSPR: NMI Mask
| #define EWIC_EVENTSPR_NMI_Pos 1U |
EWIC EVENTSPR: NMI Position
| #define EWIC_EVENTSPR_NMI_Pos 1U |
EWIC EVENTSPR: NMI Position
| #define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) |
FPDSCR: FZ16 bit Mask
| #define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) |
FPDSCR: FZ16 bit Mask
| #define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) |
FPDSCR: FZ16 bit Mask
| #define FPU_FPDSCR_FZ16_Pos 19U |
FPDSCR: FZ16 bit Position
| #define FPU_FPDSCR_FZ16_Pos 19U |
FPDSCR: FZ16 bit Position
| #define FPU_FPDSCR_FZ16_Pos 19U |
FPDSCR: FZ16 bit Position
| #define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) |
FPDSCR: LTPSIZE bit Mask
| #define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) |
FPDSCR: LTPSIZE bit Mask
| #define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) |
FPDSCR: LTPSIZE bit Mask
| #define FPU_FPDSCR_LTPSIZE_Pos 16U |
FPDSCR: LTPSIZE bit Position
| #define FPU_FPDSCR_LTPSIZE_Pos 16U |
FPDSCR: LTPSIZE bit Position
| #define FPU_FPDSCR_LTPSIZE_Pos 16U |
FPDSCR: LTPSIZE bit Position
| #define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) |
MVFR0: Divide bits Mask
| #define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) |
MVFR0: Divide bits Mask
| #define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) |
MVFR0: Divide bits Mask
| #define FPU_MVFR0_FPDivide_Pos 16U |
MVFR0: FPDivide bits Position
| #define FPU_MVFR0_FPDivide_Pos 16U |
MVFR0: FPDivide bits Position
| #define FPU_MVFR0_FPDivide_Pos 16U |
MVFR0: FPDivide bits Position
| #define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) |
MVFR0: FPDP bits Mask
| #define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) |
MVFR0: FPDP bits Mask
| #define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) |
MVFR0: FPDP bits Mask
| #define FPU_MVFR0_FPDP_Pos 8U |
MVFR0: FPDP bits Position
| #define FPU_MVFR0_FPDP_Pos 8U |
MVFR0: FPDP bits Position
| #define FPU_MVFR0_FPDP_Pos 8U |
MVFR0: FPDP bits Position
| #define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) |
MVFR0: FPRound bits Mask
| #define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) |
MVFR0: FPRound bits Mask
| #define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) |
MVFR0: FPRound bits Mask
| #define FPU_MVFR0_FPRound_Pos 28U |
MVFR0: FPRound bits Position
| #define FPU_MVFR0_FPRound_Pos 28U |
MVFR0: FPRound bits Position
| #define FPU_MVFR0_FPRound_Pos 28U |
MVFR0: FPRound bits Position
| #define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) |
MVFR0: FPSP bits Mask
| #define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) |
MVFR0: FPSP bits Mask
| #define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) |
MVFR0: FPSP bits Mask
| #define FPU_MVFR0_FPSP_Pos 4U |
MVFR0: FPSP bits Position
| #define FPU_MVFR0_FPSP_Pos 4U |
MVFR0: FPSP bits Position
| #define FPU_MVFR0_FPSP_Pos 4U |
MVFR0: FPSP bits Position
| #define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) |
MVFR0: FPSqrt bits Mask
| #define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) |
MVFR0: FPSqrt bits Mask
| #define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) |
MVFR0: FPSqrt bits Mask
| #define FPU_MVFR0_FPSqrt_Pos 20U |
MVFR0: FPSqrt bits Position
| #define FPU_MVFR0_FPSqrt_Pos 20U |
MVFR0: FPSqrt bits Position
| #define FPU_MVFR0_FPSqrt_Pos 20U |
MVFR0: FPSqrt bits Position
| #define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) |
MVFR0: SIMDReg bits Mask
| #define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) |
MVFR0: SIMDReg bits Mask
| #define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) |
MVFR0: SIMDReg bits Mask
| #define FPU_MVFR0_SIMDReg_Pos 0U |
MVFR0: SIMDReg bits Position
| #define FPU_MVFR0_SIMDReg_Pos 0U |
MVFR0: SIMDReg bits Position
| #define FPU_MVFR0_SIMDReg_Pos 0U |
MVFR0: SIMDReg bits Position
| #define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) |
MVFR1: FMAC bits Mask
| #define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) |
MVFR1: FMAC bits Mask
| #define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) |
MVFR1: FMAC bits Mask
| #define FPU_MVFR1_FMAC_Pos 28U |
MVFR1: FMAC bits Position
| #define FPU_MVFR1_FMAC_Pos 28U |
MVFR1: FMAC bits Position
| #define FPU_MVFR1_FMAC_Pos 28U |
MVFR1: FMAC bits Position
| #define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) |
MVFR1: FP16 bits Mask
| #define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) |
MVFR1: FP16 bits Mask
| #define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) |
MVFR1: FP16 bits Mask
| #define FPU_MVFR1_FP16_Pos 20U |
MVFR1: FP16 bits Position
| #define FPU_MVFR1_FP16_Pos 20U |
MVFR1: FP16 bits Position
| #define FPU_MVFR1_FP16_Pos 20U |
MVFR1: FP16 bits Position
| #define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) |
MVFR1: FPDNaN bits Mask
| #define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) |
MVFR1: FPDNaN bits Mask
| #define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) |
MVFR1: FPDNaN bits Mask
| #define FPU_MVFR1_FPDNaN_Pos 4U |
MVFR1: FPDNaN bits Position
| #define FPU_MVFR1_FPDNaN_Pos 4U |
MVFR1: FPDNaN bits Position
| #define FPU_MVFR1_FPDNaN_Pos 4U |
MVFR1: FPDNaN bits Position
| #define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) |
MVFR1: FPFtZ bits Mask
| #define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) |
MVFR1: FPFtZ bits Mask
| #define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) |
MVFR1: FPFtZ bits Mask
| #define FPU_MVFR1_FPFtZ_Pos 0U |
MVFR1: FPFtZ bits Position
| #define FPU_MVFR1_FPFtZ_Pos 0U |
MVFR1: FPFtZ bits Position
| #define FPU_MVFR1_FPFtZ_Pos 0U |
MVFR1: FPFtZ bits Position
| #define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) |
MVFR1: FPHP bits Mask
| #define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) |
MVFR1: FPHP bits Mask
| #define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) |
MVFR1: FPHP bits Mask
| #define FPU_MVFR1_FPHP_Pos 24U |
MVFR1: FPHP bits Position
| #define FPU_MVFR1_FPHP_Pos 24U |
MVFR1: FPHP bits Position
| #define FPU_MVFR1_FPHP_Pos 24U |
MVFR1: FPHP bits Position
| #define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) |
MVFR1: MVE bits Mask
| #define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) |
MVFR1: MVE bits Mask
| #define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) |
MVFR1: MVE bits Mask
| #define FPU_MVFR1_MVE_Pos 8U |
MVFR1: MVE bits Position
| #define FPU_MVFR1_MVE_Pos 8U |
MVFR1: MVE bits Position
| #define FPU_MVFR1_MVE_Pos 8U |
MVFR1: MVE bits Position
| #define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) |
ACTLR: DISCRITAXIRUR Mask
| #define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) |
ACTLR: DISCRITAXIRUR Mask
| #define ICB_ACTLR_DISCRITAXIRUR_Pos 15U |
ACTLR: DISCRITAXIRUR Position
| #define ICB_ACTLR_DISCRITAXIRUR_Pos 15U |
ACTLR: DISCRITAXIRUR Position
| #define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) |
ACTLR: DISCRITAXIRUW Mask
| #define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) |
ACTLR: DISCRITAXIRUW Mask
| #define ICB_ACTLR_DISCRITAXIRUW_Pos 27U |
ACTLR: DISCRITAXIRUW Position
| #define ICB_ACTLR_DISCRITAXIRUW_Pos 27U |
ACTLR: DISCRITAXIRUW Position
| #define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) |
ACTLR: DISITMATBFLUSH Mask
| #define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) |
ACTLR: DISITMATBFLUSH Mask
| #define ICB_ACTLR_DISITMATBFLUSH_Pos 12U |
ACTLR: DISITMATBFLUSH Position
| #define ICB_ACTLR_DISITMATBFLUSH_Pos 12U |
ACTLR: DISITMATBFLUSH Position
| #define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) |
ACTLR: DISNWAMODE Mask
| #define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) |
ACTLR: DISNWAMODE Mask
| #define ICB_ACTLR_DISNWAMODE_Pos 11U |
ACTLR: DISNWAMODE Position
| #define ICB_ACTLR_DISNWAMODE_Pos 11U |
ACTLR: DISNWAMODE Position
| #define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) |
ACTLR: EVENTBUSEN Mask
| #define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) |
ACTLR: EVENTBUSEN Mask
| #define ICB_ACTLR_EVENTBUSEN_Pos 14U |
ACTLR: EVENTBUSEN Position
| #define ICB_ACTLR_EVENTBUSEN_Pos 14U |
ACTLR: EVENTBUSEN Position
| #define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) |
ACTLR: EVENTBUSEN_S Mask
| #define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) |
ACTLR: EVENTBUSEN_S Mask
| #define ICB_ACTLR_EVENTBUSEN_S_Pos 13U |
ACTLR: EVENTBUSEN_S Position
| #define ICB_ACTLR_EVENTBUSEN_S_Pos 13U |
ACTLR: EVENTBUSEN_S Position
| #define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) |
ACTLR: FPEXCODIS Mask
| #define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) |
ACTLR: FPEXCODIS Mask
| #define ICB_ACTLR_FPEXCODIS_Pos 10U |
ACTLR: FPEXCODIS Position
| #define ICB_ACTLR_FPEXCODIS_Pos 10U |
ACTLR: FPEXCODIS Position
| #define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) |
ICTR: INTLINESNUM Mask
| #define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) |
ICTR: INTLINESNUM Mask
| #define ICB_ICTR_INTLINESNUM_Pos 0U |
ICTR: INTLINESNUM Position
| #define ICB_ICTR_INTLINESNUM_Pos 0U |
ICTR: INTLINESNUM Position
| #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) |
Memory System Control configuration struct
| #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) |
Memory System Control configuration struct
| #define MEMSYSCTL_BASE (0xE001E000UL) |
Memory System Control Base Address
| #define MEMSYSCTL_BASE (0xE001E000UL) |
Memory System Control Base Address
| #define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) |
MEMSYSCTL DTCMCR: EN Mask
| #define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) |
MEMSYSCTL DTCMCR: EN Mask
| #define MEMSYSCTL_DTCMCR_EN_Pos 0U |
MEMSYSCTL DTCMCR: EN Position
| #define MEMSYSCTL_DTCMCR_EN_Pos 0U |
MEMSYSCTL DTCMCR: EN Position
| #define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) |
MEMSYSCTL DTCMCR: SZ Mask
| #define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) |
MEMSYSCTL DTCMCR: SZ Mask
| #define MEMSYSCTL_DTCMCR_SZ_Pos 3U |
MEMSYSCTL DTCMCR: SZ Position
| #define MEMSYSCTL_DTCMCR_SZ_Pos 3U |
MEMSYSCTL DTCMCR: SZ Position
| #define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) |
MEMSYSCTL DTGU_CFG: BLKSZ Mask
| #define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) |
MEMSYSCTL DTGU_CFG: BLKSZ Mask
| #define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U |
MEMSYSCTL DTGU_CFG: BLKSZ Position
| #define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U |
MEMSYSCTL DTGU_CFG: BLKSZ Position
| #define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) |
MEMSYSCTL DTGU_CFG: NUMBLKS Mask
| #define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) |
MEMSYSCTL DTGU_CFG: NUMBLKS Mask
| #define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U |
MEMSYSCTL DTGU_CFG: NUMBLKS Position
| #define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U |
MEMSYSCTL DTGU_CFG: NUMBLKS Position
| #define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) |
MEMSYSCTL DTGU_CFG: PRESENT Mask
| #define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) |
MEMSYSCTL DTGU_CFG: PRESENT Mask
| #define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U |
MEMSYSCTL DTGU_CFG: PRESENT Position
| #define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U |
MEMSYSCTL DTGU_CFG: PRESENT Position
| #define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) |
MEMSYSCTL DTGU_CTRL: DBFEN Mask
| #define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) |
MEMSYSCTL DTGU_CTRL: DBFEN Mask
| #define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U |
MEMSYSCTL DTGU_CTRL: DBFEN Position
| #define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U |
MEMSYSCTL DTGU_CTRL: DBFEN Position
| #define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) |
MEMSYSCTL DTGU_CTRL: DEREN Mask
| #define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) |
MEMSYSCTL DTGU_CTRL: DEREN Mask
| #define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U |
MEMSYSCTL DTGU_CTRL: DEREN Position
| #define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U |
MEMSYSCTL DTGU_CTRL: DEREN Position
| #define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) |
MEMSYSCTL ITCMCR: EN Mask
| #define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) |
MEMSYSCTL ITCMCR: EN Mask
| #define MEMSYSCTL_ITCMCR_EN_Pos 0U |
MEMSYSCTL ITCMCR: EN Position
| #define MEMSYSCTL_ITCMCR_EN_Pos 0U |
MEMSYSCTL ITCMCR: EN Position
| #define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) |
MEMSYSCTL ITCMCR: SZ Mask
| #define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) |
MEMSYSCTL ITCMCR: SZ Mask
| #define MEMSYSCTL_ITCMCR_SZ_Pos 3U |
MEMSYSCTL ITCMCR: SZ Position
| #define MEMSYSCTL_ITCMCR_SZ_Pos 3U |
MEMSYSCTL ITCMCR: SZ Position
| #define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) |
MEMSYSCTL ITGU_CFG: BLKSZ Mask
| #define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) |
MEMSYSCTL ITGU_CFG: BLKSZ Mask
| #define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U |
MEMSYSCTL ITGU_CFG: BLKSZ Position
| #define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U |
MEMSYSCTL ITGU_CFG: BLKSZ Position
| #define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) |
MEMSYSCTL ITGU_CFG: NUMBLKS Mask
| #define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) |
MEMSYSCTL ITGU_CFG: NUMBLKS Mask
| #define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U |
MEMSYSCTL ITGU_CFG: NUMBLKS Position
| #define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U |
MEMSYSCTL ITGU_CFG: NUMBLKS Position
| #define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) |
MEMSYSCTL ITGU_CFG: PRESENT Mask
| #define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) |
MEMSYSCTL ITGU_CFG: PRESENT Mask
| #define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U |
MEMSYSCTL ITGU_CFG: PRESENT Position
| #define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U |
MEMSYSCTL ITGU_CFG: PRESENT Position
| #define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) |
MEMSYSCTL ITGU_CTRL: DBFEN Mask
| #define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) |
MEMSYSCTL ITGU_CTRL: DBFEN Mask
| #define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U |
MEMSYSCTL ITGU_CTRL: DBFEN Position
| #define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U |
MEMSYSCTL ITGU_CTRL: DBFEN Position
| #define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) |
MEMSYSCTL ITGU_CTRL: DEREN Mask
| #define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) |
MEMSYSCTL ITGU_CTRL: DEREN Mask
| #define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U |
MEMSYSCTL ITGU_CTRL: DEREN Position
| #define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U |
MEMSYSCTL ITGU_CTRL: DEREN Position
| #define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) |
MEMSYSCTL MSCR: CPWRDN Mask
| #define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) |
MEMSYSCTL MSCR: CPWRDN Mask
| #define MEMSYSCTL_MSCR_CPWRDN_Pos 17U |
MEMSYSCTL MSCR: CPWRDN Position
| #define MEMSYSCTL_MSCR_CPWRDN_Pos 17U |
MEMSYSCTL MSCR: CPWRDN Position
| #define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) |
MEMSYSCTL MSCR: DCACTIVE Mask
| #define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) |
MEMSYSCTL MSCR: DCACTIVE Mask
| #define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U |
MEMSYSCTL MSCR: DCACTIVE Position
| #define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U |
MEMSYSCTL MSCR: DCACTIVE Position
| #define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) |
MEMSYSCTL MSCR: DCCLEAN Mask
| #define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) |
MEMSYSCTL MSCR: DCCLEAN Mask
| #define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U |
MEMSYSCTL MSCR: DCCLEAN Position
| #define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U |
MEMSYSCTL MSCR: DCCLEAN Position
| #define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) |
MEMSYSCTL MSCR: ECCEN Mask
| #define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) |
MEMSYSCTL MSCR: ECCEN Mask
| #define MEMSYSCTL_MSCR_ECCEN_Pos 1U |
MEMSYSCTL MSCR: ECCEN Position
| #define MEMSYSCTL_MSCR_ECCEN_Pos 1U |
MEMSYSCTL MSCR: ECCEN Position
| #define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) |
MEMSYSCTL MSCR: EVECCFAULT Mask
| #define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) |
MEMSYSCTL MSCR: EVECCFAULT Mask
| #define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U |
MEMSYSCTL MSCR: EVECCFAULT Position
| #define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U |
MEMSYSCTL MSCR: EVECCFAULT Position
| #define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) |
MEMSYSCTL MSCR: FORCEWT Mask
| #define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) |
MEMSYSCTL MSCR: FORCEWT Mask
| #define MEMSYSCTL_MSCR_FORCEWT_Pos 2U |
MEMSYSCTL MSCR: FORCEWT Position
| #define MEMSYSCTL_MSCR_FORCEWT_Pos 2U |
MEMSYSCTL MSCR: FORCEWT Position
| #define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) |
MEMSYSCTL MSCR: ICACTIVE Mask
| #define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) |
MEMSYSCTL MSCR: ICACTIVE Mask
| #define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U |
MEMSYSCTL MSCR: ICACTIVE Position
| #define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U |
MEMSYSCTL MSCR: ICACTIVE Position
| #define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) |
MEMSYSCTL PAHBCR: EN Mask
| #define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) |
MEMSYSCTL PAHBCR: EN Mask
| #define MEMSYSCTL_PAHBCR_EN_Pos 0U |
MEMSYSCTL PAHBCR: EN Position
| #define MEMSYSCTL_PAHBCR_EN_Pos 0U |
MEMSYSCTL PAHBCR: EN Position
| #define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) |
MEMSYSCTL PAHBCR: SZ Mask
| #define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) |
MEMSYSCTL PAHBCR: SZ Mask
| #define MEMSYSCTL_PAHBCR_SZ_Pos 1U |
MEMSYSCTL PAHBCR: SZ Position
| #define MEMSYSCTL_PAHBCR_SZ_Pos 1U |
MEMSYSCTL PAHBCR: SZ Position
| #define MEMSYSCTL_PFCR_DIS_NLP_Msk (0x1UL << MEMSYSCTL_PFCR_DIS_NLP_Pos) |
MEMSYSCTL PFCR: DIS_NLP Mask
| #define MEMSYSCTL_PFCR_DIS_NLP_Pos 7U |
MEMSYSCTL PFCR: DIS_NLP Position
| #define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) |
MEMSYSCTL PFCR: ENABLE Mask
| #define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) |
MEMSYSCTL PFCR: ENABLE Mask
| #define MEMSYSCTL_PFCR_ENABLE_Pos 0U |
MEMSYSCTL PFCR: ENABLE Position
| #define MEMSYSCTL_PFCR_ENABLE_Pos 0U |
MEMSYSCTL PFCR: ENABLE Position
| #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) |
Processor Configuration Information configuration struct
| #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) |
Processor Configuration Information configuration struct
| #define PRCCFGINF_BASE (0xE001E700UL) |
Processor Configuration Information Base Address
| #define PRCCFGINF_BASE (0xE001E700UL) |
Processor Configuration Information Base Address
| #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) |
Power Mode Control configuration struct
| #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) |
Power Mode Control configuration struct
| #define PWRMODCTL_BASE (0xE001E300UL) |
Power Mode Control Base Address
| #define PWRMODCTL_BASE (0xE001E300UL) |
Power Mode Control Base Address
| #define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) |
PWRMODCTL CPDLPSTATE: CLPSTATE Mask
| #define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) |
PWRMODCTL CPDLPSTATE: CLPSTATE Mask
| #define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U |
PWRMODCTL CPDLPSTATE: CLPSTATE Position
| #define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U |
PWRMODCTL CPDLPSTATE: CLPSTATE Position
| #define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) |
PWRMODCTL CPDLPSTATE: ELPSTATE Mask
| #define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) |
PWRMODCTL CPDLPSTATE: ELPSTATE Mask
| #define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U |
PWRMODCTL CPDLPSTATE: ELPSTATE Position
| #define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U |
PWRMODCTL CPDLPSTATE: ELPSTATE Position
| #define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) |
PWRMODCTL CPDLPSTATE: RLPSTATE Mask
| #define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) |
PWRMODCTL CPDLPSTATE: RLPSTATE Mask
| #define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U |
PWRMODCTL CPDLPSTATE: RLPSTATE Position
| #define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U |
PWRMODCTL CPDLPSTATE: RLPSTATE Position
| #define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) |
PWRMODCTL DPDLPSTATE: DLPSTATE Mask
| #define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) |
PWRMODCTL DPDLPSTATE: DLPSTATE Mask
| #define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U |
PWRMODCTL DPDLPSTATE: DLPSTATE Position
| #define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U |
PWRMODCTL DPDLPSTATE: DLPSTATE Position
| #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) |
SCB ABFSR: AHBP Mask
| #define SCB_ABFSR_AHBP_Pos 2U |
SCB ABFSR: AHBP Position
| #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) |
SCB ABFSR: AXIM Mask
| #define SCB_ABFSR_AXIM_Pos 3U |
SCB ABFSR: AXIM Position
| #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) |
SCB ABFSR: AXIMTYPE Mask
| #define SCB_ABFSR_AXIMTYPE_Pos 8U |
SCB ABFSR: AXIMTYPE Position
| #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) |
SCB ABFSR: DTCM Mask
| #define SCB_ABFSR_DTCM_Pos 1U |
SCB ABFSR: DTCM Position
| #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) |
SCB ABFSR: EPPB Mask
| #define SCB_ABFSR_EPPB_Pos 4U |
SCB ABFSR: EPPB Position
| #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) |
SCB ABFSR: ITCM Mask
| #define SCB_ABFSR_ITCM_Pos 0U |
SCB ABFSR: ITCM Position
| #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) |
SCB AHBPCR: EN Mask
| #define SCB_AHBPCR_EN_Pos 0U |
SCB AHBPCR: EN Position
| #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) |
SCB AHBPCR: SZ Mask
| #define SCB_AHBPCR_SZ_Pos 1U |
SCB AHBPCR: SZ Position
| #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBSCR_CTL_Pos*/) |
SCB AHBSCR: CTL Mask
| #define SCB_AHBSCR_CTL_Pos 0U |
SCB AHBSCR: CTL Position
| #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBSCR_INITCOUNT_Pos) |
SCB AHBSCR: INITCOUNT Mask
| #define SCB_AHBSCR_INITCOUNT_Pos 11U |
SCB AHBSCR: INITCOUNT Position
| #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBSCR_TPRI_Pos) |
SCB AHBSCR: TPRI Mask
| #define SCB_AHBSCR_TPRI_Pos 2U |
SCB AHBSCR: TPRI Position
| #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) |
SCB AIRCR: BFHFNMINS Mask
| #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) |
SCB AIRCR: BFHFNMINS Mask
| #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) |
SCB AIRCR: BFHFNMINS Mask
| #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) |
SCB AIRCR: BFHFNMINS Mask
| #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) |
SCB AIRCR: BFHFNMINS Mask
| #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) |
SCB AIRCR: BFHFNMINS Mask
| #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) |
SCB AIRCR: BFHFNMINS Mask
| #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) |
SCB AIRCR: BFHFNMINS Mask
| #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) |
SCB AIRCR: BFHFNMINS Mask
| #define SCB_AIRCR_BFHFNMINS_Pos 13U |
SCB AIRCR: BFHFNMINS Position
| #define SCB_AIRCR_BFHFNMINS_Pos 13U |
SCB AIRCR: BFHFNMINS Position
| #define SCB_AIRCR_BFHFNMINS_Pos 13U |
SCB AIRCR: BFHFNMINS Position
| #define SCB_AIRCR_BFHFNMINS_Pos 13U |
SCB AIRCR: BFHFNMINS Position
| #define SCB_AIRCR_BFHFNMINS_Pos 13U |
SCB AIRCR: BFHFNMINS Position
| #define SCB_AIRCR_BFHFNMINS_Pos 13U |
SCB AIRCR: BFHFNMINS Position
| #define SCB_AIRCR_BFHFNMINS_Pos 13U |
SCB AIRCR: BFHFNMINS Position
| #define SCB_AIRCR_BFHFNMINS_Pos 13U |
SCB AIRCR: BFHFNMINS Position
| #define SCB_AIRCR_BFHFNMINS_Pos 13U |
SCB AIRCR: BFHFNMINS Position
| #define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) |
SCB AIRCR: Data Independent Timing Mask
| #define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) |
SCB AIRCR: Data Independent Timing Mask
| #define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) |
SCB AIRCR: Data Independent Timing Mask
| #define SCB_AIRCR_DIT_Pos 4U |
SCB AIRCR: Data Independent Timing Position
| #define SCB_AIRCR_DIT_Pos 4U |
SCB AIRCR: Data Independent Timing Position
| #define SCB_AIRCR_DIT_Pos 4U |
SCB AIRCR: Data Independent Timing Position
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
| #define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) |
SCB AIRCR: Implicit ESB Enable Mask
| #define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) |
SCB AIRCR: Implicit ESB Enable Mask
| #define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) |
SCB AIRCR: Implicit ESB Enable Mask
| #define SCB_AIRCR_IESB_Pos 5U |
SCB AIRCR: Implicit ESB Enable Position
| #define SCB_AIRCR_IESB_Pos 5U |
SCB AIRCR: Implicit ESB Enable Position
| #define SCB_AIRCR_IESB_Pos 5U |
SCB AIRCR: Implicit ESB Enable Position
| #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
SCB AIRCR: PRIGROUP Mask
| #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
SCB AIRCR: PRIGROUP Mask
| #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
SCB AIRCR: PRIGROUP Mask
| #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
SCB AIRCR: PRIGROUP Mask
| #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
SCB AIRCR: PRIGROUP Mask
| #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
SCB AIRCR: PRIGROUP Mask
| #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
SCB AIRCR: PRIGROUP Mask
| #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
SCB AIRCR: PRIGROUP Mask
| #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
SCB AIRCR: PRIGROUP Mask
| #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
SCB AIRCR: PRIGROUP Mask
| #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
SCB AIRCR: PRIGROUP Mask
| #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
SCB AIRCR: PRIGROUP Mask
| #define SCB_AIRCR_PRIGROUP_Pos 8U |
SCB AIRCR: PRIGROUP Position
| #define SCB_AIRCR_PRIGROUP_Pos 8U |
SCB AIRCR: PRIGROUP Position
| #define SCB_AIRCR_PRIGROUP_Pos 8U |
SCB AIRCR: PRIGROUP Position
| #define SCB_AIRCR_PRIGROUP_Pos 8U |
SCB AIRCR: PRIGROUP Position
| #define SCB_AIRCR_PRIGROUP_Pos 8U |
SCB AIRCR: PRIGROUP Position
| #define SCB_AIRCR_PRIGROUP_Pos 8U |
SCB AIRCR: PRIGROUP Position
| #define SCB_AIRCR_PRIGROUP_Pos 8U |
SCB AIRCR: PRIGROUP Position
| #define SCB_AIRCR_PRIGROUP_Pos 8U |
SCB AIRCR: PRIGROUP Position
| #define SCB_AIRCR_PRIGROUP_Pos 8U |
SCB AIRCR: PRIGROUP Position
| #define SCB_AIRCR_PRIGROUP_Pos 8U |
SCB AIRCR: PRIGROUP Position
| #define SCB_AIRCR_PRIGROUP_Pos 8U |
SCB AIRCR: PRIGROUP Position
| #define SCB_AIRCR_PRIGROUP_Pos 8U |
SCB AIRCR: PRIGROUP Position
| #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) |
SCB AIRCR: PRIS Mask
| #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) |
SCB AIRCR: PRIS Mask
| #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) |
SCB AIRCR: PRIS Mask
| #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) |
SCB AIRCR: PRIS Mask
| #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) |
SCB AIRCR: PRIS Mask
| #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) |
SCB AIRCR: PRIS Mask
| #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) |
SCB AIRCR: PRIS Mask
| #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) |
SCB AIRCR: PRIS Mask
| #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) |
SCB AIRCR: PRIS Mask
| #define SCB_AIRCR_PRIS_Pos 14U |
SCB AIRCR: PRIS Position
| #define SCB_AIRCR_PRIS_Pos 14U |
SCB AIRCR: PRIS Position
| #define SCB_AIRCR_PRIS_Pos 14U |
SCB AIRCR: PRIS Position
| #define SCB_AIRCR_PRIS_Pos 14U |
SCB AIRCR: PRIS Position
| #define SCB_AIRCR_PRIS_Pos 14U |
SCB AIRCR: PRIS Position
| #define SCB_AIRCR_PRIS_Pos 14U |
SCB AIRCR: PRIS Position
| #define SCB_AIRCR_PRIS_Pos 14U |
SCB AIRCR: PRIS Position
| #define SCB_AIRCR_PRIS_Pos 14U |
SCB AIRCR: PRIS Position
| #define SCB_AIRCR_PRIS_Pos 14U |
SCB AIRCR: PRIS Position
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
| #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) |
SCB AIRCR: SYSRESETREQS Mask
| #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) |
SCB AIRCR: SYSRESETREQS Mask
| #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) |
SCB AIRCR: SYSRESETREQS Mask
| #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) |
SCB AIRCR: SYSRESETREQS Mask
| #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) |
SCB AIRCR: SYSRESETREQS Mask
| #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) |
SCB AIRCR: SYSRESETREQS Mask
| #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) |
SCB AIRCR: SYSRESETREQS Mask
| #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) |
SCB AIRCR: SYSRESETREQS Mask
| #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) |
SCB AIRCR: SYSRESETREQS Mask
| #define SCB_AIRCR_SYSRESETREQS_Pos 3U |
SCB AIRCR: SYSRESETREQS Position
| #define SCB_AIRCR_SYSRESETREQS_Pos 3U |
SCB AIRCR: SYSRESETREQS Position
| #define SCB_AIRCR_SYSRESETREQS_Pos 3U |
SCB AIRCR: SYSRESETREQS Position
| #define SCB_AIRCR_SYSRESETREQS_Pos 3U |
SCB AIRCR: SYSRESETREQS Position
| #define SCB_AIRCR_SYSRESETREQS_Pos 3U |
SCB AIRCR: SYSRESETREQS Position
| #define SCB_AIRCR_SYSRESETREQS_Pos 3U |
SCB AIRCR: SYSRESETREQS Position
| #define SCB_AIRCR_SYSRESETREQS_Pos 3U |
SCB AIRCR: SYSRESETREQS Position
| #define SCB_AIRCR_SYSRESETREQS_Pos 3U |
SCB AIRCR: SYSRESETREQS Position
| #define SCB_AIRCR_SYSRESETREQS_Pos 3U |
SCB AIRCR: SYSRESETREQS Position
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
| #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) |
SCB AIRCR: VECTRESET Mask
| #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) |
SCB AIRCR: VECTRESET Mask
| #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) |
SCB AIRCR: VECTRESET Mask
| #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) |
SCB AIRCR: VECTRESET Mask
| #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) |
SCB AIRCR: VECTRESET Mask
| #define SCB_AIRCR_VECTRESET_Pos 0U |
SCB AIRCR: VECTRESET Position
| #define SCB_AIRCR_VECTRESET_Pos 0U |
SCB AIRCR: VECTRESET Position
| #define SCB_AIRCR_VECTRESET_Pos 0U |
SCB AIRCR: VECTRESET Position
| #define SCB_AIRCR_VECTRESET_Pos 0U |
SCB AIRCR: VECTRESET Position
| #define SCB_AIRCR_VECTRESET_Pos 0U |
SCB AIRCR: VECTRESET Position
| #define SCB_CACR_DCACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) |
SCB CACR: DCACTIVE Mask
| #define SCB_CACR_DCACTIVE_Pos 12U |
SCB CACR: DCACTIVE Position
| #define SCB_CACR_DCCLEAN_Msk (1UL << SCB_CACR_FORCEWT_Pos) |
SCB CACR: DCCLEAN Mask
| #define SCB_CACR_DCCLEAN_Pos 16U |
SCB CACR: DCCLEAN Position
| #define SCB_CACR_ECCDIS_Msk (1UL << SCB_CACR_ECCDIS_Pos) |
SCB CACR: ECCDIS Mask
| #define SCB_CACR_ECCDIS_Pos 1U |
SCB CACR: ECCDIS Position
| #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) |
| #define SCB_CACR_ECCEN_Pos 1U |
| #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) |
SCB CACR: FORCEWT Mask
| #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) |
SCB CACR: FORCEWT Mask
| #define SCB_CACR_FORCEWT_Pos 2U |
SCB CACR: FORCEWT Position
| #define SCB_CACR_FORCEWT_Pos 2U |
SCB CACR: FORCEWT Position
| #define SCB_CACR_ICACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) |
SCB CACR: ICACTIVE Mask
| #define SCB_CACR_ICACTIVE_Pos 13U |
SCB CACR: ICACTIVE Position
| #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) |
SCB CACR: SIWT Mask
| #define SCB_CACR_SIWT_Pos 0U |
SCB CACR: SIWT Position
| #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
SCB CCR: BFHFNMIGN Mask
| #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
SCB CCR: BFHFNMIGN Mask
| #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
SCB CCR: BFHFNMIGN Mask
| #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
SCB CCR: BFHFNMIGN Mask
| #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
SCB CCR: BFHFNMIGN Mask
| #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
SCB CCR: BFHFNMIGN Mask
| #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
SCB CCR: BFHFNMIGN Mask
| #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
SCB CCR: BFHFNMIGN Mask
| #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
SCB CCR: BFHFNMIGN Mask
| #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
SCB CCR: BFHFNMIGN Mask
| #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
SCB CCR: BFHFNMIGN Mask
| #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
SCB CCR: BFHFNMIGN Mask
| #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
SCB CCR: BFHFNMIGN Mask
| #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
SCB CCR: BFHFNMIGN Mask
| #define SCB_CCR_BFHFNMIGN_Pos 8U |
SCB CCR: BFHFNMIGN Position
| #define SCB_CCR_BFHFNMIGN_Pos 8U |
SCB CCR: BFHFNMIGN Position
| #define SCB_CCR_BFHFNMIGN_Pos 8U |
SCB CCR: BFHFNMIGN Position
| #define SCB_CCR_BFHFNMIGN_Pos 8U |
SCB CCR: BFHFNMIGN Position
| #define SCB_CCR_BFHFNMIGN_Pos 8U |
SCB CCR: BFHFNMIGN Position
| #define SCB_CCR_BFHFNMIGN_Pos 8U |
SCB CCR: BFHFNMIGN Position
| #define SCB_CCR_BFHFNMIGN_Pos 8U |
SCB CCR: BFHFNMIGN Position
| #define SCB_CCR_BFHFNMIGN_Pos 8U |
SCB CCR: BFHFNMIGN Position
| #define SCB_CCR_BFHFNMIGN_Pos 8U |
SCB CCR: BFHFNMIGN Position
| #define SCB_CCR_BFHFNMIGN_Pos 8U |
SCB CCR: BFHFNMIGN Position
| #define SCB_CCR_BFHFNMIGN_Pos 8U |
SCB CCR: BFHFNMIGN Position
| #define SCB_CCR_BFHFNMIGN_Pos 8U |
SCB CCR: BFHFNMIGN Position
| #define SCB_CCR_BFHFNMIGN_Pos 8U |
SCB CCR: BFHFNMIGN Position
| #define SCB_CCR_BFHFNMIGN_Pos 8U |
SCB CCR: BFHFNMIGN Position
| #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) |
SCB CCR: BP Mask
SCB CCR: Branch prediction enable bit Mask
| #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) |
SCB CCR: BP Mask
SCB CCR: Branch prediction enable bit Mask
| #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) |
SCB CCR: BP Mask
SCB CCR: Branch prediction enable bit Mask
| #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) |
SCB CCR: BP Mask
SCB CCR: Branch prediction enable bit Mask
| #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) |
SCB CCR: BP Mask
SCB CCR: Branch prediction enable bit Mask
| #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) |
SCB CCR: BP Mask
SCB CCR: Branch prediction enable bit Mask
| #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) |
SCB CCR: BP Mask
SCB CCR: Branch prediction enable bit Mask
| #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) |
SCB CCR: Branch prediction enable bit Mask
SCB CCR: BP Mask
| #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) |
SCB CCR: BP Mask
| #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) |
SCB CCR: BP Mask
| #define SCB_CCR_BP_Pos 18U |
SCB CCR: BP Position
SCB CCR: Branch prediction enable bit Position
| #define SCB_CCR_BP_Pos 18U |
SCB CCR: BP Position
SCB CCR: Branch prediction enable bit Position
| #define SCB_CCR_BP_Pos 18U |
SCB CCR: BP Position
SCB CCR: Branch prediction enable bit Position
| #define SCB_CCR_BP_Pos 18U |
SCB CCR: BP Position
SCB CCR: Branch prediction enable bit Position
| #define SCB_CCR_BP_Pos 18U |
SCB CCR: BP Position
SCB CCR: Branch prediction enable bit Position
| #define SCB_CCR_BP_Pos 18U |
SCB CCR: BP Position
SCB CCR: Branch prediction enable bit Position
| #define SCB_CCR_BP_Pos 18U |
SCB CCR: BP Position
SCB CCR: Branch prediction enable bit Position
| #define SCB_CCR_BP_Pos 18U |
SCB CCR: Branch prediction enable bit Position
SCB CCR: BP Position
| #define SCB_CCR_BP_Pos 18U |
SCB CCR: BP Position
| #define SCB_CCR_BP_Pos 18U |
SCB CCR: BP Position
| #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) |
SCB CCR: DC Mask
SCB CCR: Cache enable bit Mask
| #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) |
SCB CCR: DC Mask
SCB CCR: Cache enable bit Mask
| #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) |
SCB CCR: DC Mask
SCB CCR: Cache enable bit Mask
| #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) |
SCB CCR: DC Mask
SCB CCR: Cache enable bit Mask
| #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) |
SCB CCR: DC Mask
SCB CCR: Cache enable bit Mask
| #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) |
SCB CCR: DC Mask
SCB CCR: Cache enable bit Mask
| #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) |
SCB CCR: DC Mask
SCB CCR: Cache enable bit Mask
| #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) |
SCB CCR: Cache enable bit Mask
SCB CCR: DC Mask
| #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) |
SCB CCR: DC Mask
| #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) |
SCB CCR: DC Mask
| #define SCB_CCR_DC_Pos 16U |
SCB CCR: DC Position
SCB CCR: Cache enable bit Position
| #define SCB_CCR_DC_Pos 16U |
SCB CCR: DC Position
SCB CCR: Cache enable bit Position
| #define SCB_CCR_DC_Pos 16U |
SCB CCR: DC Position
SCB CCR: Cache enable bit Position
| #define SCB_CCR_DC_Pos 16U |
SCB CCR: DC Position
SCB CCR: Cache enable bit Position
| #define SCB_CCR_DC_Pos 16U |
SCB CCR: DC Position
SCB CCR: Cache enable bit Position
| #define SCB_CCR_DC_Pos 16U |
SCB CCR: DC Position
SCB CCR: Cache enable bit Position
| #define SCB_CCR_DC_Pos 16U |
SCB CCR: DC Position
SCB CCR: Cache enable bit Position
| #define SCB_CCR_DC_Pos 16U |
SCB CCR: Cache enable bit Position
SCB CCR: DC Position
| #define SCB_CCR_DC_Pos 16U |
SCB CCR: DC Position
| #define SCB_CCR_DC_Pos 16U |
SCB CCR: DC Position
| #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
SCB CCR: DIV_0_TRP Mask
| #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
SCB CCR: DIV_0_TRP Mask
| #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
SCB CCR: DIV_0_TRP Mask
| #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
SCB CCR: DIV_0_TRP Mask
| #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
SCB CCR: DIV_0_TRP Mask
| #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
SCB CCR: DIV_0_TRP Mask
| #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
SCB CCR: DIV_0_TRP Mask
| #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
SCB CCR: DIV_0_TRP Mask
| #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
SCB CCR: DIV_0_TRP Mask
| #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
SCB CCR: DIV_0_TRP Mask
| #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
SCB CCR: DIV_0_TRP Mask
| #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
SCB CCR: DIV_0_TRP Mask
| #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
SCB CCR: DIV_0_TRP Mask
| #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
SCB CCR: DIV_0_TRP Mask
| #define SCB_CCR_DIV_0_TRP_Pos 4U |
SCB CCR: DIV_0_TRP Position
| #define SCB_CCR_DIV_0_TRP_Pos 4U |
SCB CCR: DIV_0_TRP Position
| #define SCB_CCR_DIV_0_TRP_Pos 4U |
SCB CCR: DIV_0_TRP Position
| #define SCB_CCR_DIV_0_TRP_Pos 4U |
SCB CCR: DIV_0_TRP Position
| #define SCB_CCR_DIV_0_TRP_Pos 4U |
SCB CCR: DIV_0_TRP Position
| #define SCB_CCR_DIV_0_TRP_Pos 4U |
SCB CCR: DIV_0_TRP Position
| #define SCB_CCR_DIV_0_TRP_Pos 4U |
SCB CCR: DIV_0_TRP Position
| #define SCB_CCR_DIV_0_TRP_Pos 4U |
SCB CCR: DIV_0_TRP Position
| #define SCB_CCR_DIV_0_TRP_Pos 4U |
SCB CCR: DIV_0_TRP Position
| #define SCB_CCR_DIV_0_TRP_Pos 4U |
SCB CCR: DIV_0_TRP Position
| #define SCB_CCR_DIV_0_TRP_Pos 4U |
SCB CCR: DIV_0_TRP Position
| #define SCB_CCR_DIV_0_TRP_Pos 4U |
SCB CCR: DIV_0_TRP Position
| #define SCB_CCR_DIV_0_TRP_Pos 4U |
SCB CCR: DIV_0_TRP Position
| #define SCB_CCR_DIV_0_TRP_Pos 4U |
SCB CCR: DIV_0_TRP Position
| #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) |
SCB CCR: IC Mask
SCB CCR: Instruction cache enable bit Mask
| #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) |
SCB CCR: IC Mask
SCB CCR: Instruction cache enable bit Mask
| #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) |
SCB CCR: IC Mask
SCB CCR: Instruction cache enable bit Mask
| #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) |
SCB CCR: IC Mask
SCB CCR: Instruction cache enable bit Mask
| #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) |
SCB CCR: IC Mask
SCB CCR: Instruction cache enable bit Mask
| #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) |
SCB CCR: IC Mask
SCB CCR: Instruction cache enable bit Mask
| #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) |
SCB CCR: IC Mask
SCB CCR: Instruction cache enable bit Mask
| #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) |
SCB CCR: Instruction cache enable bit Mask
SCB CCR: IC Mask
| #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) |
SCB CCR: IC Mask
| #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) |
SCB CCR: IC Mask
| #define SCB_CCR_IC_Pos 17U |
SCB CCR: IC Position
SCB CCR: Instruction cache enable bit Position
| #define SCB_CCR_IC_Pos 17U |
SCB CCR: IC Position
SCB CCR: Instruction cache enable bit Position
| #define SCB_CCR_IC_Pos 17U |
SCB CCR: IC Position
SCB CCR: Instruction cache enable bit Position
| #define SCB_CCR_IC_Pos 17U |
SCB CCR: IC Position
SCB CCR: Instruction cache enable bit Position
| #define SCB_CCR_IC_Pos 17U |
SCB CCR: IC Position
SCB CCR: Instruction cache enable bit Position
| #define SCB_CCR_IC_Pos 17U |
SCB CCR: IC Position
SCB CCR: Instruction cache enable bit Position
| #define SCB_CCR_IC_Pos 17U |
SCB CCR: IC Position
SCB CCR: Instruction cache enable bit Position
| #define SCB_CCR_IC_Pos 17U |
SCB CCR: Instruction cache enable bit Position
SCB CCR: IC Position
| #define SCB_CCR_IC_Pos 17U |
SCB CCR: IC Position
| #define SCB_CCR_IC_Pos 17U |
SCB CCR: IC Position
| #define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) |
SCB CCR: LOB Mask
| #define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) |
SCB CCR: LOB Mask
| #define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) |
SCB CCR: LOB Mask
| #define SCB_CCR_LOB_Pos 19U |
SCB CCR: LOB Position
| #define SCB_CCR_LOB_Pos 19U |
SCB CCR: LOB Position
| #define SCB_CCR_LOB_Pos 19U |
SCB CCR: LOB Position
| #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) |
SCB CCR: NONBASETHRDENA Mask
| #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) |
SCB CCR: NONBASETHRDENA Mask
| #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) |
SCB CCR: NONBASETHRDENA Mask
| #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) |
SCB CCR: NONBASETHRDENA Mask
| #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) |
SCB CCR: NONBASETHRDENA Mask
| #define SCB_CCR_NONBASETHRDENA_Pos 0U |
SCB CCR: NONBASETHRDENA Position
| #define SCB_CCR_NONBASETHRDENA_Pos 0U |
SCB CCR: NONBASETHRDENA Position
| #define SCB_CCR_NONBASETHRDENA_Pos 0U |
SCB CCR: NONBASETHRDENA Position
| #define SCB_CCR_NONBASETHRDENA_Pos 0U |
SCB CCR: NONBASETHRDENA Position
| #define SCB_CCR_NONBASETHRDENA_Pos 0U |
SCB CCR: NONBASETHRDENA Position
| #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) |
SCB CCR: STKALIGN Mask
| #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) |
SCB CCR: STKALIGN Mask
| #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) |
SCB CCR: STKALIGN Mask
| #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) |
SCB CCR: STKALIGN Mask
| #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) |
SCB CCR: STKALIGN Mask
| #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) |
SCB CCR: STKALIGN Mask
| #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) |
SCB CCR: STKALIGN Mask
| #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) |
SCB CCR: STKALIGN Mask
| #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) |
SCB CCR: STKALIGN Mask
| #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) |
SCB CCR: STKALIGN Mask
| #define SCB_CCR_STKALIGN_Pos 9U |
SCB CCR: STKALIGN Position
| #define SCB_CCR_STKALIGN_Pos 9U |
SCB CCR: STKALIGN Position
| #define SCB_CCR_STKALIGN_Pos 9U |
SCB CCR: STKALIGN Position
| #define SCB_CCR_STKALIGN_Pos 9U |
SCB CCR: STKALIGN Position
| #define SCB_CCR_STKALIGN_Pos 9U |
SCB CCR: STKALIGN Position
| #define SCB_CCR_STKALIGN_Pos 9U |
SCB CCR: STKALIGN Position
| #define SCB_CCR_STKALIGN_Pos 9U |
SCB CCR: STKALIGN Position
| #define SCB_CCR_STKALIGN_Pos 9U |
SCB CCR: STKALIGN Position
| #define SCB_CCR_STKALIGN_Pos 9U |
SCB CCR: STKALIGN Position
| #define SCB_CCR_STKALIGN_Pos 9U |
SCB CCR: STKALIGN Position
| #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) |
SCB CCR: STKOFHFNMIGN Mask
| #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) |
SCB CCR: STKOFHFNMIGN Mask
| #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) |
SCB CCR: STKOFHFNMIGN Mask
| #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) |
SCB CCR: STKOFHFNMIGN Mask
| #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) |
SCB CCR: STKOFHFNMIGN Mask
| #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) |
SCB CCR: STKOFHFNMIGN Mask
| #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) |
SCB CCR: STKOFHFNMIGN Mask
| #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) |
SCB CCR: STKOFHFNMIGN Mask
| #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) |
SCB CCR: STKOFHFNMIGN Mask
| #define SCB_CCR_STKOFHFNMIGN_Pos 10U |
SCB CCR: STKOFHFNMIGN Position
| #define SCB_CCR_STKOFHFNMIGN_Pos 10U |
SCB CCR: STKOFHFNMIGN Position
| #define SCB_CCR_STKOFHFNMIGN_Pos 10U |
SCB CCR: STKOFHFNMIGN Position
| #define SCB_CCR_STKOFHFNMIGN_Pos 10U |
SCB CCR: STKOFHFNMIGN Position
| #define SCB_CCR_STKOFHFNMIGN_Pos 10U |
SCB CCR: STKOFHFNMIGN Position
| #define SCB_CCR_STKOFHFNMIGN_Pos 10U |
SCB CCR: STKOFHFNMIGN Position
| #define SCB_CCR_STKOFHFNMIGN_Pos 10U |
SCB CCR: STKOFHFNMIGN Position
| #define SCB_CCR_STKOFHFNMIGN_Pos 10U |
SCB CCR: STKOFHFNMIGN Position
| #define SCB_CCR_STKOFHFNMIGN_Pos 10U |
SCB CCR: STKOFHFNMIGN Position
| #define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) |
SCB CCR: TRD Mask
| #define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) |
SCB CCR: TRD Mask
| #define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) |
SCB CCR: TRD Mask
| #define SCB_CCR_TRD_Pos 20U |
SCB CCR: TRD Position
| #define SCB_CCR_TRD_Pos 20U |
SCB CCR: TRD Position
| #define SCB_CCR_TRD_Pos 20U |
SCB CCR: TRD Position
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
| #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
SCB CCR: USERSETMPEND Mask
| #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
SCB CCR: USERSETMPEND Mask
| #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
SCB CCR: USERSETMPEND Mask
| #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
SCB CCR: USERSETMPEND Mask
| #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
SCB CCR: USERSETMPEND Mask
| #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
SCB CCR: USERSETMPEND Mask
| #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
SCB CCR: USERSETMPEND Mask
| #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
SCB CCR: USERSETMPEND Mask
| #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
SCB CCR: USERSETMPEND Mask
| #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
SCB CCR: USERSETMPEND Mask
| #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
SCB CCR: USERSETMPEND Mask
| #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
SCB CCR: USERSETMPEND Mask
| #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
SCB CCR: USERSETMPEND Mask
| #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
SCB CCR: USERSETMPEND Mask
| #define SCB_CCR_USERSETMPEND_Pos 1U |
SCB CCR: USERSETMPEND Position
| #define SCB_CCR_USERSETMPEND_Pos 1U |
SCB CCR: USERSETMPEND Position
| #define SCB_CCR_USERSETMPEND_Pos 1U |
SCB CCR: USERSETMPEND Position
| #define SCB_CCR_USERSETMPEND_Pos 1U |
SCB CCR: USERSETMPEND Position
| #define SCB_CCR_USERSETMPEND_Pos 1U |
SCB CCR: USERSETMPEND Position
| #define SCB_CCR_USERSETMPEND_Pos 1U |
SCB CCR: USERSETMPEND Position
| #define SCB_CCR_USERSETMPEND_Pos 1U |
SCB CCR: USERSETMPEND Position
| #define SCB_CCR_USERSETMPEND_Pos 1U |
SCB CCR: USERSETMPEND Position
| #define SCB_CCR_USERSETMPEND_Pos 1U |
SCB CCR: USERSETMPEND Position
| #define SCB_CCR_USERSETMPEND_Pos 1U |
SCB CCR: USERSETMPEND Position
| #define SCB_CCR_USERSETMPEND_Pos 1U |
SCB CCR: USERSETMPEND Position
| #define SCB_CCR_USERSETMPEND_Pos 1U |
SCB CCR: USERSETMPEND Position
| #define SCB_CCR_USERSETMPEND_Pos 1U |
SCB CCR: USERSETMPEND Position
| #define SCB_CCR_USERSETMPEND_Pos 1U |
SCB CCR: USERSETMPEND Position
| #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) |
SCB CCSIDR: Associativity Mask
| #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) |
SCB CCSIDR: Associativity Mask
| #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) |
SCB CCSIDR: Associativity Mask
| #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) |
SCB CCSIDR: Associativity Mask
| #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) |
SCB CCSIDR: Associativity Mask
| #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) |
SCB CCSIDR: Associativity Mask
| #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) |
SCB CCSIDR: Associativity Mask
| #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) |
SCB CCSIDR: Associativity Mask
| #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U |
SCB CCSIDR: Associativity Position
| #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U |
SCB CCSIDR: Associativity Position
| #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U |
SCB CCSIDR: Associativity Position
| #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U |
SCB CCSIDR: Associativity Position
| #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U |
SCB CCSIDR: Associativity Position
| #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U |
SCB CCSIDR: Associativity Position
| #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U |
SCB CCSIDR: Associativity Position
| #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U |
SCB CCSIDR: Associativity Position
| #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) |
SCB CCSIDR: LineSize Mask
| #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) |
SCB CCSIDR: LineSize Mask
| #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) |
SCB CCSIDR: LineSize Mask
| #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) |
SCB CCSIDR: LineSize Mask
| #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) |
SCB CCSIDR: LineSize Mask
| #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) |
SCB CCSIDR: LineSize Mask
| #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) |
SCB CCSIDR: LineSize Mask
| #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) |
SCB CCSIDR: LineSize Mask
| #define SCB_CCSIDR_LINESIZE_Pos 0U |
SCB CCSIDR: LineSize Position
| #define SCB_CCSIDR_LINESIZE_Pos 0U |
SCB CCSIDR: LineSize Position
| #define SCB_CCSIDR_LINESIZE_Pos 0U |
SCB CCSIDR: LineSize Position
| #define SCB_CCSIDR_LINESIZE_Pos 0U |
SCB CCSIDR: LineSize Position
| #define SCB_CCSIDR_LINESIZE_Pos 0U |
SCB CCSIDR: LineSize Position
| #define SCB_CCSIDR_LINESIZE_Pos 0U |
SCB CCSIDR: LineSize Position
| #define SCB_CCSIDR_LINESIZE_Pos 0U |
SCB CCSIDR: LineSize Position
| #define SCB_CCSIDR_LINESIZE_Pos 0U |
SCB CCSIDR: LineSize Position
| #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) |
SCB CCSIDR: NumSets Mask
| #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) |
SCB CCSIDR: NumSets Mask
| #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) |
SCB CCSIDR: NumSets Mask
| #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) |
SCB CCSIDR: NumSets Mask
| #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) |
SCB CCSIDR: NumSets Mask
| #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) |
SCB CCSIDR: NumSets Mask
| #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) |
SCB CCSIDR: NumSets Mask
| #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) |
SCB CCSIDR: NumSets Mask
| #define SCB_CCSIDR_NUMSETS_Pos 13U |
SCB CCSIDR: NumSets Position
| #define SCB_CCSIDR_NUMSETS_Pos 13U |
SCB CCSIDR: NumSets Position
| #define SCB_CCSIDR_NUMSETS_Pos 13U |
SCB CCSIDR: NumSets Position
| #define SCB_CCSIDR_NUMSETS_Pos 13U |
SCB CCSIDR: NumSets Position
| #define SCB_CCSIDR_NUMSETS_Pos 13U |
SCB CCSIDR: NumSets Position
| #define SCB_CCSIDR_NUMSETS_Pos 13U |
SCB CCSIDR: NumSets Position
| #define SCB_CCSIDR_NUMSETS_Pos 13U |
SCB CCSIDR: NumSets Position
| #define SCB_CCSIDR_NUMSETS_Pos 13U |
SCB CCSIDR: NumSets Position
| #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) |
SCB CCSIDR: RA Mask
| #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) |
SCB CCSIDR: RA Mask
| #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) |
SCB CCSIDR: RA Mask
| #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) |
SCB CCSIDR: RA Mask
| #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) |
SCB CCSIDR: RA Mask
| #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) |
SCB CCSIDR: RA Mask
| #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) |
SCB CCSIDR: RA Mask
| #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) |
SCB CCSIDR: RA Mask
| #define SCB_CCSIDR_RA_Pos 29U |
SCB CCSIDR: RA Position
| #define SCB_CCSIDR_RA_Pos 29U |
SCB CCSIDR: RA Position
| #define SCB_CCSIDR_RA_Pos 29U |
SCB CCSIDR: RA Position
| #define SCB_CCSIDR_RA_Pos 29U |
SCB CCSIDR: RA Position
| #define SCB_CCSIDR_RA_Pos 29U |
SCB CCSIDR: RA Position
| #define SCB_CCSIDR_RA_Pos 29U |
SCB CCSIDR: RA Position
| #define SCB_CCSIDR_RA_Pos 29U |
SCB CCSIDR: RA Position
| #define SCB_CCSIDR_RA_Pos 29U |
SCB CCSIDR: RA Position
| #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) |
SCB CCSIDR: WA Mask
| #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) |
SCB CCSIDR: WA Mask
| #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) |
SCB CCSIDR: WA Mask
| #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) |
SCB CCSIDR: WA Mask
| #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) |
SCB CCSIDR: WA Mask
| #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) |
SCB CCSIDR: WA Mask
| #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) |
SCB CCSIDR: WA Mask
| #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) |
SCB CCSIDR: WA Mask
| #define SCB_CCSIDR_WA_Pos 28U |
SCB CCSIDR: WA Position
| #define SCB_CCSIDR_WA_Pos 28U |
SCB CCSIDR: WA Position
| #define SCB_CCSIDR_WA_Pos 28U |
SCB CCSIDR: WA Position
| #define SCB_CCSIDR_WA_Pos 28U |
SCB CCSIDR: WA Position
| #define SCB_CCSIDR_WA_Pos 28U |
SCB CCSIDR: WA Position
| #define SCB_CCSIDR_WA_Pos 28U |
SCB CCSIDR: WA Position
| #define SCB_CCSIDR_WA_Pos 28U |
SCB CCSIDR: WA Position
| #define SCB_CCSIDR_WA_Pos 28U |
SCB CCSIDR: WA Position
| #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) |
SCB CCSIDR: WB Mask
| #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) |
SCB CCSIDR: WB Mask
| #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) |
SCB CCSIDR: WB Mask
| #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) |
SCB CCSIDR: WB Mask
| #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) |
SCB CCSIDR: WB Mask
| #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) |
SCB CCSIDR: WB Mask
| #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) |
SCB CCSIDR: WB Mask
| #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) |
SCB CCSIDR: WB Mask
| #define SCB_CCSIDR_WB_Pos 30U |
SCB CCSIDR: WB Position
| #define SCB_CCSIDR_WB_Pos 30U |
SCB CCSIDR: WB Position
| #define SCB_CCSIDR_WB_Pos 30U |
SCB CCSIDR: WB Position
| #define SCB_CCSIDR_WB_Pos 30U |
SCB CCSIDR: WB Position
| #define SCB_CCSIDR_WB_Pos 30U |
SCB CCSIDR: WB Position
| #define SCB_CCSIDR_WB_Pos 30U |
SCB CCSIDR: WB Position
| #define SCB_CCSIDR_WB_Pos 30U |
SCB CCSIDR: WB Position
| #define SCB_CCSIDR_WB_Pos 30U |
SCB CCSIDR: WB Position
| #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) |
SCB CCSIDR: WT Mask
| #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) |
SCB CCSIDR: WT Mask
| #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) |
SCB CCSIDR: WT Mask
| #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) |
SCB CCSIDR: WT Mask
| #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) |
SCB CCSIDR: WT Mask
| #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) |
SCB CCSIDR: WT Mask
| #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) |
SCB CCSIDR: WT Mask
| #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) |
SCB CCSIDR: WT Mask
| #define SCB_CCSIDR_WT_Pos 31U |
SCB CCSIDR: WT Position
| #define SCB_CCSIDR_WT_Pos 31U |
SCB CCSIDR: WT Position
| #define SCB_CCSIDR_WT_Pos 31U |
SCB CCSIDR: WT Position
| #define SCB_CCSIDR_WT_Pos 31U |
SCB CCSIDR: WT Position
| #define SCB_CCSIDR_WT_Pos 31U |
SCB CCSIDR: WT Position
| #define SCB_CCSIDR_WT_Pos 31U |
SCB CCSIDR: WT Position
| #define SCB_CCSIDR_WT_Pos 31U |
SCB CCSIDR: WT Position
| #define SCB_CCSIDR_WT_Pos 31U |
SCB CCSIDR: WT Position
| #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) |
SCB CFSR (BFSR): BFARVALID Mask
| #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) |
SCB CFSR (BFSR): BFARVALID Mask
| #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) |
SCB CFSR (BFSR): BFARVALID Mask
| #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) |
SCB CFSR (BFSR): BFARVALID Mask
| #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) |
SCB CFSR (BFSR): BFARVALID Mask
| #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) |
SCB CFSR (BFSR): BFARVALID Mask
| #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) |
SCB CFSR (BFSR): BFARVALID Mask
| #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) |
SCB CFSR (BFSR): BFARVALID Mask
| #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) |
SCB CFSR (BFSR): BFARVALID Mask
| #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) |
SCB CFSR (BFSR): BFARVALID Mask
| #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) |
SCB CFSR (BFSR): BFARVALID Mask
| #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) |
SCB CFSR (BFSR): BFARVALID Mask
| #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) |
SCB CFSR (BFSR): BFARVALID Position
| #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) |
SCB CFSR (BFSR): BFARVALID Position
| #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) |
SCB CFSR (BFSR): BFARVALID Position
| #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) |
SCB CFSR (BFSR): BFARVALID Position
| #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) |
SCB CFSR (BFSR): BFARVALID Position
| #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) |
SCB CFSR (BFSR): BFARVALID Position
| #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) |
SCB CFSR (BFSR): BFARVALID Position
| #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) |
SCB CFSR (BFSR): BFARVALID Position
| #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) |
SCB CFSR (BFSR): BFARVALID Position
| #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) |
SCB CFSR (BFSR): BFARVALID Position
| #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) |
SCB CFSR (BFSR): BFARVALID Position
| #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) |
SCB CFSR (BFSR): BFARVALID Position
| #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
SCB CFSR: Bus Fault Status Register Mask
| #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
SCB CFSR: Bus Fault Status Register Mask
| #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
SCB CFSR: Bus Fault Status Register Mask
| #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
SCB CFSR: Bus Fault Status Register Mask
| #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
SCB CFSR: Bus Fault Status Register Mask
| #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
SCB CFSR: Bus Fault Status Register Mask
| #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
SCB CFSR: Bus Fault Status Register Mask
| #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
SCB CFSR: Bus Fault Status Register Mask
| #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
SCB CFSR: Bus Fault Status Register Mask
| #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
SCB CFSR: Bus Fault Status Register Mask
| #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
SCB CFSR: Bus Fault Status Register Mask
| #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
SCB CFSR: Bus Fault Status Register Mask
| #define SCB_CFSR_BUSFAULTSR_Pos 8U |
SCB CFSR: Bus Fault Status Register Position
| #define SCB_CFSR_BUSFAULTSR_Pos 8U |
SCB CFSR: Bus Fault Status Register Position
| #define SCB_CFSR_BUSFAULTSR_Pos 8U |
SCB CFSR: Bus Fault Status Register Position
| #define SCB_CFSR_BUSFAULTSR_Pos 8U |
SCB CFSR: Bus Fault Status Register Position
| #define SCB_CFSR_BUSFAULTSR_Pos 8U |
SCB CFSR: Bus Fault Status Register Position
| #define SCB_CFSR_BUSFAULTSR_Pos 8U |
SCB CFSR: Bus Fault Status Register Position
| #define SCB_CFSR_BUSFAULTSR_Pos 8U |
SCB CFSR: Bus Fault Status Register Position
| #define SCB_CFSR_BUSFAULTSR_Pos 8U |
SCB CFSR: Bus Fault Status Register Position
| #define SCB_CFSR_BUSFAULTSR_Pos 8U |
SCB CFSR: Bus Fault Status Register Position
| #define SCB_CFSR_BUSFAULTSR_Pos 8U |
SCB CFSR: Bus Fault Status Register Position
| #define SCB_CFSR_BUSFAULTSR_Pos 8U |
SCB CFSR: Bus Fault Status Register Position
| #define SCB_CFSR_BUSFAULTSR_Pos 8U |
SCB CFSR: Bus Fault Status Register Position
| #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) |
SCB CFSR (MMFSR): DACCVIOL Mask
| #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) |
SCB CFSR (MMFSR): DACCVIOL Mask
| #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) |
SCB CFSR (MMFSR): DACCVIOL Mask
| #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) |
SCB CFSR (MMFSR): DACCVIOL Mask
| #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) |
SCB CFSR (MMFSR): DACCVIOL Mask
| #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) |
SCB CFSR (MMFSR): DACCVIOL Mask
| #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) |
SCB CFSR (MMFSR): DACCVIOL Mask
| #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) |
SCB CFSR (MMFSR): DACCVIOL Mask
| #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) |
SCB CFSR (MMFSR): DACCVIOL Mask
| #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) |
SCB CFSR (MMFSR): DACCVIOL Mask
| #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) |
SCB CFSR (MMFSR): DACCVIOL Mask
| #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) |
SCB CFSR (MMFSR): DACCVIOL Mask
| #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) |
SCB CFSR (MMFSR): DACCVIOL Position
| #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) |
SCB CFSR (MMFSR): DACCVIOL Position
| #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) |
SCB CFSR (MMFSR): DACCVIOL Position
| #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) |
SCB CFSR (MMFSR): DACCVIOL Position
| #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) |
SCB CFSR (MMFSR): DACCVIOL Position
| #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) |
SCB CFSR (MMFSR): DACCVIOL Position
| #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) |
SCB CFSR (MMFSR): DACCVIOL Position
| #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) |
SCB CFSR (MMFSR): DACCVIOL Position
| #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) |
SCB CFSR (MMFSR): DACCVIOL Position
| #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) |
SCB CFSR (MMFSR): DACCVIOL Position
| #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) |
SCB CFSR (MMFSR): DACCVIOL Position
| #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) |
SCB CFSR (MMFSR): DACCVIOL Position
| #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) |
SCB CFSR (UFSR): DIVBYZERO Mask
| #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) |
SCB CFSR (UFSR): DIVBYZERO Mask
| #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) |
SCB CFSR (UFSR): DIVBYZERO Mask
| #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) |
SCB CFSR (UFSR): DIVBYZERO Mask
| #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) |
SCB CFSR (UFSR): DIVBYZERO Mask
| #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) |
SCB CFSR (UFSR): DIVBYZERO Mask
| #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) |
SCB CFSR (UFSR): DIVBYZERO Mask
| #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) |
SCB CFSR (UFSR): DIVBYZERO Mask
| #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) |
SCB CFSR (UFSR): DIVBYZERO Mask
| #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) |
SCB CFSR (UFSR): DIVBYZERO Mask
| #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) |
SCB CFSR (UFSR): DIVBYZERO Mask
| #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) |
SCB CFSR (UFSR): DIVBYZERO Mask
| #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) |
SCB CFSR (UFSR): DIVBYZERO Position
| #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) |
SCB CFSR (UFSR): DIVBYZERO Position
| #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) |
SCB CFSR (UFSR): DIVBYZERO Position
| #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) |
SCB CFSR (UFSR): DIVBYZERO Position
| #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) |
SCB CFSR (UFSR): DIVBYZERO Position
| #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) |
SCB CFSR (UFSR): DIVBYZERO Position
| #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) |
SCB CFSR (UFSR): DIVBYZERO Position
| #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) |
SCB CFSR (UFSR): DIVBYZERO Position
| #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) |
SCB CFSR (UFSR): DIVBYZERO Position
| #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) |
SCB CFSR (UFSR): DIVBYZERO Position
| #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) |
SCB CFSR (UFSR): DIVBYZERO Position
| #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) |
SCB CFSR (UFSR): DIVBYZERO Position
| #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) |
SCB CFSR (MMFSR): IACCVIOL Mask
| #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) |
SCB CFSR (MMFSR): IACCVIOL Mask
| #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) |
SCB CFSR (MMFSR): IACCVIOL Mask
| #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) |
SCB CFSR (MMFSR): IACCVIOL Mask
| #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) |
SCB CFSR (MMFSR): IACCVIOL Mask
| #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) |
SCB CFSR (MMFSR): IACCVIOL Mask
| #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) |
SCB CFSR (MMFSR): IACCVIOL Mask
| #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) |
SCB CFSR (MMFSR): IACCVIOL Mask
| #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) |
SCB CFSR (MMFSR): IACCVIOL Mask
| #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) |
SCB CFSR (MMFSR): IACCVIOL Mask
| #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) |
SCB CFSR (MMFSR): IACCVIOL Mask
| #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) |
SCB CFSR (MMFSR): IACCVIOL Mask
| #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) |
SCB CFSR (MMFSR): IACCVIOL Position
| #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) |
SCB CFSR (MMFSR): IACCVIOL Position
| #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) |
SCB CFSR (MMFSR): IACCVIOL Position
| #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) |
SCB CFSR (MMFSR): IACCVIOL Position
| #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) |
SCB CFSR (MMFSR): IACCVIOL Position
| #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) |
SCB CFSR (MMFSR): IACCVIOL Position
| #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) |
SCB CFSR (MMFSR): IACCVIOL Position
| #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) |
SCB CFSR (MMFSR): IACCVIOL Position
| #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) |
SCB CFSR (MMFSR): IACCVIOL Position
| #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) |
SCB CFSR (MMFSR): IACCVIOL Position
| #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) |
SCB CFSR (MMFSR): IACCVIOL Position
| #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) |
SCB CFSR (MMFSR): IACCVIOL Position
| #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) |
SCB CFSR (BFSR): IBUSERR Mask
| #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) |
SCB CFSR (BFSR): IBUSERR Mask
| #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) |
SCB CFSR (BFSR): IBUSERR Mask
| #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) |
SCB CFSR (BFSR): IBUSERR Mask
| #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) |
SCB CFSR (BFSR): IBUSERR Mask
| #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) |
SCB CFSR (BFSR): IBUSERR Mask
| #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) |
SCB CFSR (BFSR): IBUSERR Mask
| #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) |
SCB CFSR (BFSR): IBUSERR Mask
| #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) |
SCB CFSR (BFSR): IBUSERR Mask
| #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) |
SCB CFSR (BFSR): IBUSERR Mask
| #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) |
SCB CFSR (BFSR): IBUSERR Mask
| #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) |
SCB CFSR (BFSR): IBUSERR Mask
| #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) |
SCB CFSR (BFSR): IBUSERR Position
| #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) |
SCB CFSR (BFSR): IBUSERR Position
| #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) |
SCB CFSR (BFSR): IBUSERR Position
| #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) |
SCB CFSR (BFSR): IBUSERR Position
| #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) |
SCB CFSR (BFSR): IBUSERR Position
| #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) |
SCB CFSR (BFSR): IBUSERR Position
| #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) |
SCB CFSR (BFSR): IBUSERR Position
| #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) |
SCB CFSR (BFSR): IBUSERR Position
| #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) |
SCB CFSR (BFSR): IBUSERR Position
| #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) |
SCB CFSR (BFSR): IBUSERR Position
| #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) |
SCB CFSR (BFSR): IBUSERR Position
| #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) |
SCB CFSR (BFSR): IBUSERR Position
| #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) |
SCB CFSR (BFSR): IMPRECISERR Mask
| #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) |
SCB CFSR (BFSR): IMPRECISERR Mask
| #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) |
SCB CFSR (BFSR): IMPRECISERR Mask
| #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) |
SCB CFSR (BFSR): IMPRECISERR Mask
| #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) |
SCB CFSR (BFSR): IMPRECISERR Mask
| #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) |
SCB CFSR (BFSR): IMPRECISERR Mask
| #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) |
SCB CFSR (BFSR): IMPRECISERR Mask
| #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) |
SCB CFSR (BFSR): IMPRECISERR Mask
| #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) |
SCB CFSR (BFSR): IMPRECISERR Mask
| #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) |
SCB CFSR (BFSR): IMPRECISERR Mask
| #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) |
SCB CFSR (BFSR): IMPRECISERR Mask
| #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) |
SCB CFSR (BFSR): IMPRECISERR Mask
| #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) |
SCB CFSR (BFSR): IMPRECISERR Position
| #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) |
SCB CFSR (BFSR): IMPRECISERR Position
| #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) |
SCB CFSR (BFSR): IMPRECISERR Position
| #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) |
SCB CFSR (BFSR): IMPRECISERR Position
| #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) |
SCB CFSR (BFSR): IMPRECISERR Position
| #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) |
SCB CFSR (BFSR): IMPRECISERR Position
| #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) |
SCB CFSR (BFSR): IMPRECISERR Position
| #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) |
SCB CFSR (BFSR): IMPRECISERR Position
| #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) |
SCB CFSR (BFSR): IMPRECISERR Position
| #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) |
SCB CFSR (BFSR): IMPRECISERR Position
| #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) |
SCB CFSR (BFSR): IMPRECISERR Position
| #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) |
SCB CFSR (BFSR): IMPRECISERR Position
| #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) |
SCB CFSR (UFSR): INVPC Mask
| #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) |
SCB CFSR (UFSR): INVPC Mask
| #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) |
SCB CFSR (UFSR): INVPC Mask
| #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) |
SCB CFSR (UFSR): INVPC Mask
| #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) |
SCB CFSR (UFSR): INVPC Mask
| #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) |
SCB CFSR (UFSR): INVPC Mask
| #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) |
SCB CFSR (UFSR): INVPC Mask
| #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) |
SCB CFSR (UFSR): INVPC Mask
| #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) |
SCB CFSR (UFSR): INVPC Mask
| #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) |
SCB CFSR (UFSR): INVPC Mask
| #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) |
SCB CFSR (UFSR): INVPC Mask
| #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) |
SCB CFSR (UFSR): INVPC Mask
| #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) |
SCB CFSR (UFSR): INVPC Position
| #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) |
SCB CFSR (UFSR): INVPC Position
| #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) |
SCB CFSR (UFSR): INVPC Position
| #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) |
SCB CFSR (UFSR): INVPC Position
| #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) |
SCB CFSR (UFSR): INVPC Position
| #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) |
SCB CFSR (UFSR): INVPC Position
| #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) |
SCB CFSR (UFSR): INVPC Position
| #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) |
SCB CFSR (UFSR): INVPC Position
| #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) |
SCB CFSR (UFSR): INVPC Position
| #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) |
SCB CFSR (UFSR): INVPC Position
| #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) |
SCB CFSR (UFSR): INVPC Position
| #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) |
SCB CFSR (UFSR): INVPC Position
| #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) |
SCB CFSR (UFSR): INVSTATE Mask
| #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) |
SCB CFSR (UFSR): INVSTATE Mask
| #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) |
SCB CFSR (UFSR): INVSTATE Mask
| #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) |
SCB CFSR (UFSR): INVSTATE Mask
| #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) |
SCB CFSR (UFSR): INVSTATE Mask
| #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) |
SCB CFSR (UFSR): INVSTATE Mask
| #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) |
SCB CFSR (UFSR): INVSTATE Mask
| #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) |
SCB CFSR (UFSR): INVSTATE Mask
| #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) |
SCB CFSR (UFSR): INVSTATE Mask
| #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) |
SCB CFSR (UFSR): INVSTATE Mask
| #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) |
SCB CFSR (UFSR): INVSTATE Mask
| #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) |
SCB CFSR (UFSR): INVSTATE Mask
| #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) |
SCB CFSR (UFSR): INVSTATE Position
| #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) |
SCB CFSR (UFSR): INVSTATE Position
| #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) |
SCB CFSR (UFSR): INVSTATE Position
| #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) |
SCB CFSR (UFSR): INVSTATE Position
| #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) |
SCB CFSR (UFSR): INVSTATE Position
| #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) |
SCB CFSR (UFSR): INVSTATE Position
| #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) |
SCB CFSR (UFSR): INVSTATE Position
| #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) |
SCB CFSR (UFSR): INVSTATE Position
| #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) |
SCB CFSR (UFSR): INVSTATE Position
| #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) |
SCB CFSR (UFSR): INVSTATE Position
| #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) |
SCB CFSR (UFSR): INVSTATE Position
| #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) |
SCB CFSR (UFSR): INVSTATE Position
| #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) |
SCB CFSR (BFSR): LSPERR Mask
| #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) |
SCB CFSR (BFSR): LSPERR Mask
| #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) |
SCB CFSR (BFSR): LSPERR Mask
| #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) |
SCB CFSR (BFSR): LSPERR Mask
| #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) |
SCB CFSR (BFSR): LSPERR Mask
| #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) |
SCB CFSR (BFSR): LSPERR Mask
| #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) |
SCB CFSR (BFSR): LSPERR Mask
| #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) |
SCB CFSR (BFSR): LSPERR Mask
| #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) |
SCB CFSR (BFSR): LSPERR Mask
| #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) |
SCB CFSR (BFSR): LSPERR Position
| #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) |
SCB CFSR (BFSR): LSPERR Position
| #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) |
SCB CFSR (BFSR): LSPERR Position
| #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) |
SCB CFSR (BFSR): LSPERR Position
| #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) |
SCB CFSR (BFSR): LSPERR Position
| #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) |
SCB CFSR (BFSR): LSPERR Position
| #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) |
SCB CFSR (BFSR): LSPERR Position
| #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) |
SCB CFSR (BFSR): LSPERR Position
| #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) |
SCB CFSR (BFSR): LSPERR Position
| #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) |
SCB CFSR: Memory Manage Fault Status Register Mask
| #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) |
SCB CFSR: Memory Manage Fault Status Register Mask
| #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) |
SCB CFSR: Memory Manage Fault Status Register Mask
| #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) |
SCB CFSR: Memory Manage Fault Status Register Mask
| #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) |
SCB CFSR: Memory Manage Fault Status Register Mask
| #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) |
SCB CFSR: Memory Manage Fault Status Register Mask
| #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) |
SCB CFSR: Memory Manage Fault Status Register Mask
| #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) |
SCB CFSR: Memory Manage Fault Status Register Mask
| #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) |
SCB CFSR: Memory Manage Fault Status Register Mask
| #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) |
SCB CFSR: Memory Manage Fault Status Register Mask
| #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) |
SCB CFSR: Memory Manage Fault Status Register Mask
| #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) |
SCB CFSR: Memory Manage Fault Status Register Mask
| #define SCB_CFSR_MEMFAULTSR_Pos 0U |
SCB CFSR: Memory Manage Fault Status Register Position
| #define SCB_CFSR_MEMFAULTSR_Pos 0U |
SCB CFSR: Memory Manage Fault Status Register Position
| #define SCB_CFSR_MEMFAULTSR_Pos 0U |
SCB CFSR: Memory Manage Fault Status Register Position
| #define SCB_CFSR_MEMFAULTSR_Pos 0U |
SCB CFSR: Memory Manage Fault Status Register Position
| #define SCB_CFSR_MEMFAULTSR_Pos 0U |
SCB CFSR: Memory Manage Fault Status Register Position
| #define SCB_CFSR_MEMFAULTSR_Pos 0U |
SCB CFSR: Memory Manage Fault Status Register Position
| #define SCB_CFSR_MEMFAULTSR_Pos 0U |
SCB CFSR: Memory Manage Fault Status Register Position
| #define SCB_CFSR_MEMFAULTSR_Pos 0U |
SCB CFSR: Memory Manage Fault Status Register Position
| #define SCB_CFSR_MEMFAULTSR_Pos 0U |
SCB CFSR: Memory Manage Fault Status Register Position
| #define SCB_CFSR_MEMFAULTSR_Pos 0U |
SCB CFSR: Memory Manage Fault Status Register Position
| #define SCB_CFSR_MEMFAULTSR_Pos 0U |
SCB CFSR: Memory Manage Fault Status Register Position
| #define SCB_CFSR_MEMFAULTSR_Pos 0U |
SCB CFSR: Memory Manage Fault Status Register Position
| #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) |
SCB CFSR (MMFSR): MLSPERR Mask
| #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) |
SCB CFSR (MMFSR): MLSPERR Mask
| #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) |
SCB CFSR (MMFSR): MLSPERR Mask
| #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) |
SCB CFSR (MMFSR): MLSPERR Mask
| #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) |
SCB CFSR (MMFSR): MLSPERR Mask
| #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) |
SCB CFSR (MMFSR): MLSPERR Mask
| #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) |
SCB CFSR (MMFSR): MLSPERR Mask
| #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) |
SCB CFSR (MMFSR): MLSPERR Mask
| #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) |
SCB CFSR (MMFSR): MLSPERR Mask
| #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) |
SCB CFSR (MMFSR): MLSPERR Position
| #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) |
SCB CFSR (MMFSR): MLSPERR Position
| #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) |
SCB CFSR (MMFSR): MLSPERR Position
| #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) |
SCB CFSR (MMFSR): MLSPERR Position
| #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) |
SCB CFSR (MMFSR): MLSPERR Position
| #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) |
SCB CFSR (MMFSR): MLSPERR Position
| #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) |
SCB CFSR (MMFSR): MLSPERR Position
| #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) |
SCB CFSR (MMFSR): MLSPERR Position
| #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) |
SCB CFSR (MMFSR): MLSPERR Position
| #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) |
SCB CFSR (MMFSR): MMARVALID Mask
| #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) |
SCB CFSR (MMFSR): MMARVALID Mask
| #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) |
SCB CFSR (MMFSR): MMARVALID Mask
| #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) |
SCB CFSR (MMFSR): MMARVALID Mask
| #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) |
SCB CFSR (MMFSR): MMARVALID Mask
| #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) |
SCB CFSR (MMFSR): MMARVALID Mask
| #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) |
SCB CFSR (MMFSR): MMARVALID Mask
| #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) |
SCB CFSR (MMFSR): MMARVALID Mask
| #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) |
SCB CFSR (MMFSR): MMARVALID Mask
| #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) |
SCB CFSR (MMFSR): MMARVALID Mask
| #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) |
SCB CFSR (MMFSR): MMARVALID Mask
| #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) |
SCB CFSR (MMFSR): MMARVALID Mask
| #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) |
SCB CFSR (MMFSR): MMARVALID Position
| #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) |
SCB CFSR (MMFSR): MMARVALID Position
| #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) |
SCB CFSR (MMFSR): MMARVALID Position
| #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) |
SCB CFSR (MMFSR): MMARVALID Position
| #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) |
SCB CFSR (MMFSR): MMARVALID Position
| #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) |
SCB CFSR (MMFSR): MMARVALID Position
| #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) |
SCB CFSR (MMFSR): MMARVALID Position
| #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) |
SCB CFSR (MMFSR): MMARVALID Position
| #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) |
SCB CFSR (MMFSR): MMARVALID Position
| #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) |
SCB CFSR (MMFSR): MMARVALID Position
| #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) |
SCB CFSR (MMFSR): MMARVALID Position
| #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) |
SCB CFSR (MMFSR): MMARVALID Position
| #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) |
SCB CFSR (MMFSR): MSTKERR Mask
| #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) |
SCB CFSR (MMFSR): MSTKERR Mask
| #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) |
SCB CFSR (MMFSR): MSTKERR Mask
| #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) |
SCB CFSR (MMFSR): MSTKERR Mask
| #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) |
SCB CFSR (MMFSR): MSTKERR Mask
| #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) |
SCB CFSR (MMFSR): MSTKERR Mask
| #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) |
SCB CFSR (MMFSR): MSTKERR Mask
| #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) |
SCB CFSR (MMFSR): MSTKERR Mask
| #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) |
SCB CFSR (MMFSR): MSTKERR Mask
| #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) |
SCB CFSR (MMFSR): MSTKERR Mask
| #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) |
SCB CFSR (MMFSR): MSTKERR Mask
| #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) |
SCB CFSR (MMFSR): MSTKERR Mask
| #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) |
SCB CFSR (MMFSR): MSTKERR Position
| #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) |
SCB CFSR (MMFSR): MSTKERR Position
| #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) |
SCB CFSR (MMFSR): MSTKERR Position
| #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) |
SCB CFSR (MMFSR): MSTKERR Position
| #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) |
SCB CFSR (MMFSR): MSTKERR Position
| #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) |
SCB CFSR (MMFSR): MSTKERR Position
| #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) |
SCB CFSR (MMFSR): MSTKERR Position
| #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) |
SCB CFSR (MMFSR): MSTKERR Position
| #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) |
SCB CFSR (MMFSR): MSTKERR Position
| #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) |
SCB CFSR (MMFSR): MSTKERR Position
| #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) |
SCB CFSR (MMFSR): MSTKERR Position
| #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) |
SCB CFSR (MMFSR): MSTKERR Position
| #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) |
SCB CFSR (MMFSR): MUNSTKERR Mask
| #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) |
SCB CFSR (MMFSR): MUNSTKERR Mask
| #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) |
SCB CFSR (MMFSR): MUNSTKERR Mask
| #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) |
SCB CFSR (MMFSR): MUNSTKERR Mask
| #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) |
SCB CFSR (MMFSR): MUNSTKERR Mask
| #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) |
SCB CFSR (MMFSR): MUNSTKERR Mask
| #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) |
SCB CFSR (MMFSR): MUNSTKERR Mask
| #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) |
SCB CFSR (MMFSR): MUNSTKERR Mask
| #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) |
SCB CFSR (MMFSR): MUNSTKERR Mask
| #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) |
SCB CFSR (MMFSR): MUNSTKERR Mask
| #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) |
SCB CFSR (MMFSR): MUNSTKERR Mask
| #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) |
SCB CFSR (MMFSR): MUNSTKERR Mask
| #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) |
SCB CFSR (MMFSR): MUNSTKERR Position
| #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) |
SCB CFSR (MMFSR): MUNSTKERR Position
| #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) |
SCB CFSR (MMFSR): MUNSTKERR Position
| #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) |
SCB CFSR (MMFSR): MUNSTKERR Position
| #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) |
SCB CFSR (MMFSR): MUNSTKERR Position
| #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) |
SCB CFSR (MMFSR): MUNSTKERR Position
| #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) |
SCB CFSR (MMFSR): MUNSTKERR Position
| #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) |
SCB CFSR (MMFSR): MUNSTKERR Position
| #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) |
SCB CFSR (MMFSR): MUNSTKERR Position
| #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) |
SCB CFSR (MMFSR): MUNSTKERR Position
| #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) |
SCB CFSR (MMFSR): MUNSTKERR Position
| #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) |
SCB CFSR (MMFSR): MUNSTKERR Position
| #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) |
SCB CFSR (UFSR): NOCP Mask
| #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) |
SCB CFSR (UFSR): NOCP Mask
| #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) |
SCB CFSR (UFSR): NOCP Mask
| #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) |
SCB CFSR (UFSR): NOCP Mask
| #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) |
SCB CFSR (UFSR): NOCP Mask
| #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) |
SCB CFSR (UFSR): NOCP Mask
| #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) |
SCB CFSR (UFSR): NOCP Mask
| #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) |
SCB CFSR (UFSR): NOCP Mask
| #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) |
SCB CFSR (UFSR): NOCP Mask
| #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) |
SCB CFSR (UFSR): NOCP Mask
| #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) |
SCB CFSR (UFSR): NOCP Mask
| #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) |
SCB CFSR (UFSR): NOCP Mask
| #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) |
SCB CFSR (UFSR): NOCP Position
| #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) |
SCB CFSR (UFSR): NOCP Position
| #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) |
SCB CFSR (UFSR): NOCP Position
| #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) |
SCB CFSR (UFSR): NOCP Position
| #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) |
SCB CFSR (UFSR): NOCP Position
| #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) |
SCB CFSR (UFSR): NOCP Position
| #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) |
SCB CFSR (UFSR): NOCP Position
| #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) |
SCB CFSR (UFSR): NOCP Position
| #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) |
SCB CFSR (UFSR): NOCP Position
| #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) |
SCB CFSR (UFSR): NOCP Position
| #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) |
SCB CFSR (UFSR): NOCP Position
| #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) |
SCB CFSR (UFSR): NOCP Position
| #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) |
SCB CFSR (BFSR): PRECISERR Mask
| #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) |
SCB CFSR (BFSR): PRECISERR Mask
| #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) |
SCB CFSR (BFSR): PRECISERR Mask
| #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) |
SCB CFSR (BFSR): PRECISERR Mask
| #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) |
SCB CFSR (BFSR): PRECISERR Mask
| #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) |
SCB CFSR (BFSR): PRECISERR Mask
| #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) |
SCB CFSR (BFSR): PRECISERR Mask
| #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) |
SCB CFSR (BFSR): PRECISERR Mask
| #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) |
SCB CFSR (BFSR): PRECISERR Mask
| #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) |
SCB CFSR (BFSR): PRECISERR Mask
| #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) |
SCB CFSR (BFSR): PRECISERR Mask
| #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) |
SCB CFSR (BFSR): PRECISERR Mask
| #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) |
SCB CFSR (BFSR): PRECISERR Position
| #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) |
SCB CFSR (BFSR): PRECISERR Position
| #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) |
SCB CFSR (BFSR): PRECISERR Position
| #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) |
SCB CFSR (BFSR): PRECISERR Position
| #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) |
SCB CFSR (BFSR): PRECISERR Position
| #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) |
SCB CFSR (BFSR): PRECISERR Position
| #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) |
SCB CFSR (BFSR): PRECISERR Position
| #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) |
SCB CFSR (BFSR): PRECISERR Position
| #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) |
SCB CFSR (BFSR): PRECISERR Position
| #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) |
SCB CFSR (BFSR): PRECISERR Position
| #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) |
SCB CFSR (BFSR): PRECISERR Position
| #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) |
SCB CFSR (BFSR): PRECISERR Position
| #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) |
SCB CFSR (BFSR): STKERR Mask
| #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) |
SCB CFSR (BFSR): STKERR Mask
| #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) |
SCB CFSR (BFSR): STKERR Mask
| #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) |
SCB CFSR (BFSR): STKERR Mask
| #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) |
SCB CFSR (BFSR): STKERR Mask
| #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) |
SCB CFSR (BFSR): STKERR Mask
| #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) |
SCB CFSR (BFSR): STKERR Mask
| #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) |
SCB CFSR (BFSR): STKERR Mask
| #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) |
SCB CFSR (BFSR): STKERR Mask
| #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) |
SCB CFSR (BFSR): STKERR Mask
| #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) |
SCB CFSR (BFSR): STKERR Mask
| #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) |
SCB CFSR (BFSR): STKERR Mask
| #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) |
SCB CFSR (BFSR): STKERR Position
| #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) |
SCB CFSR (BFSR): STKERR Position
| #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) |
SCB CFSR (BFSR): STKERR Position
| #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) |
SCB CFSR (BFSR): STKERR Position
| #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) |
SCB CFSR (BFSR): STKERR Position
| #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) |
SCB CFSR (BFSR): STKERR Position
| #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) |
SCB CFSR (BFSR): STKERR Position
| #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) |
SCB CFSR (BFSR): STKERR Position
| #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) |
SCB CFSR (BFSR): STKERR Position
| #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) |
SCB CFSR (BFSR): STKERR Position
| #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) |
SCB CFSR (BFSR): STKERR Position
| #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) |
SCB CFSR (BFSR): STKERR Position
| #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) |
SCB CFSR (UFSR): STKOF Mask
| #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) |
SCB CFSR (UFSR): STKOF Mask
| #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) |
SCB CFSR (UFSR): STKOF Mask
| #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) |
SCB CFSR (UFSR): STKOF Mask
| #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) |
SCB CFSR (UFSR): STKOF Mask
| #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) |
SCB CFSR (UFSR): STKOF Mask
| #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) |
SCB CFSR (UFSR): STKOF Mask
| #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) |
SCB CFSR (UFSR): STKOF Position
| #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) |
SCB CFSR (UFSR): STKOF Position
| #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) |
SCB CFSR (UFSR): STKOF Position
| #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) |
SCB CFSR (UFSR): STKOF Position
| #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) |
SCB CFSR (UFSR): STKOF Position
| #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) |
SCB CFSR (UFSR): STKOF Position
| #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) |
SCB CFSR (UFSR): STKOF Position
| #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) |
SCB CFSR (UFSR): UNALIGNED Mask
| #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) |
SCB CFSR (UFSR): UNALIGNED Mask
| #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) |
SCB CFSR (UFSR): UNALIGNED Mask
| #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) |
SCB CFSR (UFSR): UNALIGNED Mask
| #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) |
SCB CFSR (UFSR): UNALIGNED Mask
| #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) |
SCB CFSR (UFSR): UNALIGNED Mask
| #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) |
SCB CFSR (UFSR): UNALIGNED Mask
| #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) |
SCB CFSR (UFSR): UNALIGNED Mask
| #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) |
SCB CFSR (UFSR): UNALIGNED Mask
| #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) |
SCB CFSR (UFSR): UNALIGNED Mask
| #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) |
SCB CFSR (UFSR): UNALIGNED Mask
| #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) |
SCB CFSR (UFSR): UNALIGNED Mask
| #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) |
SCB CFSR (UFSR): UNALIGNED Position
| #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) |
SCB CFSR (UFSR): UNALIGNED Position
| #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) |
SCB CFSR (UFSR): UNALIGNED Position
| #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) |
SCB CFSR (UFSR): UNALIGNED Position
| #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) |
SCB CFSR (UFSR): UNALIGNED Position
| #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) |
SCB CFSR (UFSR): UNALIGNED Position
| #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) |
SCB CFSR (UFSR): UNALIGNED Position
| #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) |
SCB CFSR (UFSR): UNALIGNED Position
| #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) |
SCB CFSR (UFSR): UNALIGNED Position
| #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) |
SCB CFSR (UFSR): UNALIGNED Position
| #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) |
SCB CFSR (UFSR): UNALIGNED Position
| #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) |
SCB CFSR (UFSR): UNALIGNED Position
| #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) |
SCB CFSR (UFSR): UNDEFINSTR Mask
| #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) |
SCB CFSR (UFSR): UNDEFINSTR Mask
| #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) |
SCB CFSR (UFSR): UNDEFINSTR Mask
| #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) |
SCB CFSR (UFSR): UNDEFINSTR Mask
| #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) |
SCB CFSR (UFSR): UNDEFINSTR Mask
| #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) |
SCB CFSR (UFSR): UNDEFINSTR Mask
| #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) |
SCB CFSR (UFSR): UNDEFINSTR Mask
| #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) |
SCB CFSR (UFSR): UNDEFINSTR Mask
| #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) |
SCB CFSR (UFSR): UNDEFINSTR Mask
| #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) |
SCB CFSR (UFSR): UNDEFINSTR Mask
| #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) |
SCB CFSR (UFSR): UNDEFINSTR Mask
| #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) |
SCB CFSR (UFSR): UNDEFINSTR Mask
| #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) |
SCB CFSR (UFSR): UNDEFINSTR Position
| #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) |
SCB CFSR (UFSR): UNDEFINSTR Position
| #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) |
SCB CFSR (UFSR): UNDEFINSTR Position
| #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) |
SCB CFSR (UFSR): UNDEFINSTR Position
| #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) |
SCB CFSR (UFSR): UNDEFINSTR Position
| #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) |
SCB CFSR (UFSR): UNDEFINSTR Position
| #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) |
SCB CFSR (UFSR): UNDEFINSTR Position
| #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) |
SCB CFSR (UFSR): UNDEFINSTR Position
| #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) |
SCB CFSR (UFSR): UNDEFINSTR Position
| #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) |
SCB CFSR (UFSR): UNDEFINSTR Position
| #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) |
SCB CFSR (UFSR): UNDEFINSTR Position
| #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) |
SCB CFSR (UFSR): UNDEFINSTR Position
| #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) |
SCB CFSR (BFSR): UNSTKERR Mask
| #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) |
SCB CFSR (BFSR): UNSTKERR Mask
| #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) |
SCB CFSR (BFSR): UNSTKERR Mask
| #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) |
SCB CFSR (BFSR): UNSTKERR Mask
| #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) |
SCB CFSR (BFSR): UNSTKERR Mask
| #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) |
SCB CFSR (BFSR): UNSTKERR Mask
| #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) |
SCB CFSR (BFSR): UNSTKERR Mask
| #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) |
SCB CFSR (BFSR): UNSTKERR Mask
| #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) |
SCB CFSR (BFSR): UNSTKERR Mask
| #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) |
SCB CFSR (BFSR): UNSTKERR Mask
| #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) |
SCB CFSR (BFSR): UNSTKERR Mask
| #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) |
SCB CFSR (BFSR): UNSTKERR Mask
| #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) |
SCB CFSR (BFSR): UNSTKERR Position
| #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) |
SCB CFSR (BFSR): UNSTKERR Position
| #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) |
SCB CFSR (BFSR): UNSTKERR Position
| #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) |
SCB CFSR (BFSR): UNSTKERR Position
| #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) |
SCB CFSR (BFSR): UNSTKERR Position
| #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) |
SCB CFSR (BFSR): UNSTKERR Position
| #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) |
SCB CFSR (BFSR): UNSTKERR Position
| #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) |
SCB CFSR (BFSR): UNSTKERR Position
| #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) |
SCB CFSR (BFSR): UNSTKERR Position
| #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) |
SCB CFSR (BFSR): UNSTKERR Position
| #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) |
SCB CFSR (BFSR): UNSTKERR Position
| #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) |
SCB CFSR (BFSR): UNSTKERR Position
| #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
SCB CFSR: Usage Fault Status Register Mask
| #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
SCB CFSR: Usage Fault Status Register Mask
| #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
SCB CFSR: Usage Fault Status Register Mask
| #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
SCB CFSR: Usage Fault Status Register Mask
| #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
SCB CFSR: Usage Fault Status Register Mask
| #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
SCB CFSR: Usage Fault Status Register Mask
| #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
SCB CFSR: Usage Fault Status Register Mask
| #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
SCB CFSR: Usage Fault Status Register Mask
| #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
SCB CFSR: Usage Fault Status Register Mask
| #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
SCB CFSR: Usage Fault Status Register Mask
| #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
SCB CFSR: Usage Fault Status Register Mask
| #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
SCB CFSR: Usage Fault Status Register Mask
| #define SCB_CFSR_USGFAULTSR_Pos 16U |
SCB CFSR: Usage Fault Status Register Position
| #define SCB_CFSR_USGFAULTSR_Pos 16U |
SCB CFSR: Usage Fault Status Register Position
| #define SCB_CFSR_USGFAULTSR_Pos 16U |
SCB CFSR: Usage Fault Status Register Position
| #define SCB_CFSR_USGFAULTSR_Pos 16U |
SCB CFSR: Usage Fault Status Register Position
| #define SCB_CFSR_USGFAULTSR_Pos 16U |
SCB CFSR: Usage Fault Status Register Position
| #define SCB_CFSR_USGFAULTSR_Pos 16U |
SCB CFSR: Usage Fault Status Register Position
| #define SCB_CFSR_USGFAULTSR_Pos 16U |
SCB CFSR: Usage Fault Status Register Position
| #define SCB_CFSR_USGFAULTSR_Pos 16U |
SCB CFSR: Usage Fault Status Register Position
| #define SCB_CFSR_USGFAULTSR_Pos 16U |
SCB CFSR: Usage Fault Status Register Position
| #define SCB_CFSR_USGFAULTSR_Pos 16U |
SCB CFSR: Usage Fault Status Register Position
| #define SCB_CFSR_USGFAULTSR_Pos 16U |
SCB CFSR: Usage Fault Status Register Position
| #define SCB_CFSR_USGFAULTSR_Pos 16U |
SCB CFSR: Usage Fault Status Register Position
| #define SCB_CLIDR_DC_Msk (1UL << SCB_CLIDR_DC_Pos) |
SCB CLIDR: DC Mask
| #define SCB_CLIDR_DC_Pos 1U |
SCB CLIDR: DC Position
| #define SCB_CLIDR_IC_Msk (1UL << SCB_CLIDR_IC_Pos) |
SCB CLIDR: IC Mask
| #define SCB_CLIDR_IC_Pos 0U |
SCB CLIDR: IC Position
| #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) |
SCB CLIDR: LoC Mask
| #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) |
SCB CLIDR: LoC Mask
| #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) |
SCB CLIDR: LoC Mask
| #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) |
SCB CLIDR: LoC Mask
| #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) |
SCB CLIDR: LoC Mask
| #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) |
SCB CLIDR: LoC Mask
| #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) |
SCB CLIDR: LoC Mask
| #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) |
SCB CLIDR: LoC Mask
| #define SCB_CLIDR_LOC_Pos 24U |
SCB CLIDR: LoC Position
| #define SCB_CLIDR_LOC_Pos 24U |
SCB CLIDR: LoC Position
| #define SCB_CLIDR_LOC_Pos 24U |
SCB CLIDR: LoC Position
| #define SCB_CLIDR_LOC_Pos 24U |
SCB CLIDR: LoC Position
| #define SCB_CLIDR_LOC_Pos 24U |
SCB CLIDR: LoC Position
| #define SCB_CLIDR_LOC_Pos 24U |
SCB CLIDR: LoC Position
| #define SCB_CLIDR_LOC_Pos 24U |
SCB CLIDR: LoC Position
| #define SCB_CLIDR_LOC_Pos 24U |
SCB CLIDR: LoC Position
| #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) |
SCB CLIDR: LoUU Mask
| #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) |
SCB CLIDR: LoUU Mask
| #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) |
SCB CLIDR: LoUU Mask
| #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) |
SCB CLIDR: LoUU Mask
| #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) |
SCB CLIDR: LoUU Mask
| #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) |
SCB CLIDR: LoUU Mask
| #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) |
SCB CLIDR: LoUU Mask
| #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) |
SCB CLIDR: LoUU Mask
| #define SCB_CLIDR_LOUU_Pos 27U |
SCB CLIDR: LoUU Position
| #define SCB_CLIDR_LOUU_Pos 27U |
SCB CLIDR: LoUU Position
| #define SCB_CLIDR_LOUU_Pos 27U |
SCB CLIDR: LoUU Position
| #define SCB_CLIDR_LOUU_Pos 27U |
SCB CLIDR: LoUU Position
| #define SCB_CLIDR_LOUU_Pos 27U |
SCB CLIDR: LoUU Position
| #define SCB_CLIDR_LOUU_Pos 27U |
SCB CLIDR: LoUU Position
| #define SCB_CLIDR_LOUU_Pos 27U |
SCB CLIDR: LoUU Position
| #define SCB_CLIDR_LOUU_Pos 27U |
SCB CLIDR: LoUU Position
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
| #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) |
SCB CSSELR: InD Mask
| #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) |
SCB CSSELR: InD Mask
| #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) |
SCB CSSELR: InD Mask
| #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) |
SCB CSSELR: InD Mask
| #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) |
SCB CSSELR: InD Mask
| #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) |
SCB CSSELR: InD Mask
| #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) |
SCB CSSELR: InD Mask
| #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) |
SCB CSSELR: InD Mask
| #define SCB_CSSELR_IND_Pos 0U |
SCB CSSELR: InD Position
| #define SCB_CSSELR_IND_Pos 0U |
SCB CSSELR: InD Position
| #define SCB_CSSELR_IND_Pos 0U |
SCB CSSELR: InD Position
| #define SCB_CSSELR_IND_Pos 0U |
SCB CSSELR: InD Position
| #define SCB_CSSELR_IND_Pos 0U |
SCB CSSELR: InD Position
| #define SCB_CSSELR_IND_Pos 0U |
SCB CSSELR: InD Position
| #define SCB_CSSELR_IND_Pos 0U |
SCB CSSELR: InD Position
| #define SCB_CSSELR_IND_Pos 0U |
SCB CSSELR: InD Position
| #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) |
SCB CSSELR: Level Mask
| #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) |
SCB CSSELR: Level Mask
| #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) |
SCB CSSELR: Level Mask
| #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) |
SCB CSSELR: Level Mask
| #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) |
SCB CSSELR: Level Mask
| #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) |
SCB CSSELR: Level Mask
| #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) |
SCB CSSELR: Level Mask
| #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) |
SCB CSSELR: Level Mask
| #define SCB_CSSELR_LEVEL_Pos 1U |
SCB CSSELR: Level Position
| #define SCB_CSSELR_LEVEL_Pos 1U |
SCB CSSELR: Level Position
| #define SCB_CSSELR_LEVEL_Pos 1U |
SCB CSSELR: Level Position
| #define SCB_CSSELR_LEVEL_Pos 1U |
SCB CSSELR: Level Position
| #define SCB_CSSELR_LEVEL_Pos 1U |
SCB CSSELR: Level Position
| #define SCB_CSSELR_LEVEL_Pos 1U |
SCB CSSELR: Level Position
| #define SCB_CSSELR_LEVEL_Pos 1U |
SCB CSSELR: Level Position
| #define SCB_CSSELR_LEVEL_Pos 1U |
SCB CSSELR: Level Position
| #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) |
SCB CTR: CWG Mask
| #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) |
SCB CTR: CWG Mask
| #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) |
SCB CTR: CWG Mask
| #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) |
SCB CTR: CWG Mask
| #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) |
SCB CTR: CWG Mask
| #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) |
SCB CTR: CWG Mask
| #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) |
SCB CTR: CWG Mask
| #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) |
SCB CTR: CWG Mask
| #define SCB_CTR_CWG_Pos 24U |
SCB CTR: CWG Position
| #define SCB_CTR_CWG_Pos 24U |
SCB CTR: CWG Position
| #define SCB_CTR_CWG_Pos 24U |
SCB CTR: CWG Position
| #define SCB_CTR_CWG_Pos 24U |
SCB CTR: CWG Position
| #define SCB_CTR_CWG_Pos 24U |
SCB CTR: CWG Position
| #define SCB_CTR_CWG_Pos 24U |
SCB CTR: CWG Position
| #define SCB_CTR_CWG_Pos 24U |
SCB CTR: CWG Position
| #define SCB_CTR_CWG_Pos 24U |
SCB CTR: CWG Position
| #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) |
SCB CTR: DminLine Mask
| #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) |
SCB CTR: DminLine Mask
| #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) |
SCB CTR: DminLine Mask
| #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) |
SCB CTR: DminLine Mask
| #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) |
SCB CTR: DminLine Mask
| #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) |
SCB CTR: DminLine Mask
| #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) |
SCB CTR: DminLine Mask
| #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) |
SCB CTR: DminLine Mask
| #define SCB_CTR_DMINLINE_Pos 16U |
SCB CTR: DminLine Position
| #define SCB_CTR_DMINLINE_Pos 16U |
SCB CTR: DminLine Position
| #define SCB_CTR_DMINLINE_Pos 16U |
SCB CTR: DminLine Position
| #define SCB_CTR_DMINLINE_Pos 16U |
SCB CTR: DminLine Position
| #define SCB_CTR_DMINLINE_Pos 16U |
SCB CTR: DminLine Position
| #define SCB_CTR_DMINLINE_Pos 16U |
SCB CTR: DminLine Position
| #define SCB_CTR_DMINLINE_Pos 16U |
SCB CTR: DminLine Position
| #define SCB_CTR_DMINLINE_Pos 16U |
SCB CTR: DminLine Position
| #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) |
SCB CTR: ERG Mask
| #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) |
SCB CTR: ERG Mask
| #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) |
SCB CTR: ERG Mask
| #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) |
SCB CTR: ERG Mask
| #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) |
SCB CTR: ERG Mask
| #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) |
SCB CTR: ERG Mask
| #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) |
SCB CTR: ERG Mask
| #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) |
SCB CTR: ERG Mask
| #define SCB_CTR_ERG_Pos 20U |
SCB CTR: ERG Position
| #define SCB_CTR_ERG_Pos 20U |
SCB CTR: ERG Position
| #define SCB_CTR_ERG_Pos 20U |
SCB CTR: ERG Position
| #define SCB_CTR_ERG_Pos 20U |
SCB CTR: ERG Position
| #define SCB_CTR_ERG_Pos 20U |
SCB CTR: ERG Position
| #define SCB_CTR_ERG_Pos 20U |
SCB CTR: ERG Position
| #define SCB_CTR_ERG_Pos 20U |
SCB CTR: ERG Position
| #define SCB_CTR_ERG_Pos 20U |
SCB CTR: ERG Position
| #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) |
SCB CTR: Format Mask
| #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) |
SCB CTR: Format Mask
| #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) |
SCB CTR: Format Mask
| #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) |
SCB CTR: Format Mask
| #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) |
SCB CTR: Format Mask
| #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) |
SCB CTR: Format Mask
| #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) |
SCB CTR: Format Mask
| #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) |
SCB CTR: Format Mask
| #define SCB_CTR_FORMAT_Pos 29U |
SCB CTR: Format Position
| #define SCB_CTR_FORMAT_Pos 29U |
SCB CTR: Format Position
| #define SCB_CTR_FORMAT_Pos 29U |
SCB CTR: Format Position
| #define SCB_CTR_FORMAT_Pos 29U |
SCB CTR: Format Position
| #define SCB_CTR_FORMAT_Pos 29U |
SCB CTR: Format Position
| #define SCB_CTR_FORMAT_Pos 29U |
SCB CTR: Format Position
| #define SCB_CTR_FORMAT_Pos 29U |
SCB CTR: Format Position
| #define SCB_CTR_FORMAT_Pos 29U |
SCB CTR: Format Position
| #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) |
SCB CTR: ImInLine Mask
| #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) |
SCB CTR: ImInLine Mask
| #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) |
SCB CTR: ImInLine Mask
| #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) |
SCB CTR: ImInLine Mask
| #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) |
SCB CTR: ImInLine Mask
| #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) |
SCB CTR: ImInLine Mask
| #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) |
SCB CTR: ImInLine Mask
| #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) |
SCB CTR: ImInLine Mask
| #define SCB_CTR_IMINLINE_Pos 0U |
SCB CTR: ImInLine Position
| #define SCB_CTR_IMINLINE_Pos 0U |
SCB CTR: ImInLine Position
| #define SCB_CTR_IMINLINE_Pos 0U |
SCB CTR: ImInLine Position
| #define SCB_CTR_IMINLINE_Pos 0U |
SCB CTR: ImInLine Position
| #define SCB_CTR_IMINLINE_Pos 0U |
SCB CTR: ImInLine Position
| #define SCB_CTR_IMINLINE_Pos 0U |
SCB CTR: ImInLine Position
| #define SCB_CTR_IMINLINE_Pos 0U |
SCB CTR: ImInLine Position
| #define SCB_CTR_IMINLINE_Pos 0U |
SCB CTR: ImInLine Position
| #define SCB_DCCISW_LEVEL_Msk (7UL << SCB_DCCISW_LEVEL_Pos) |
SCB DCCISW: Level Mask
| #define SCB_DCCISW_LEVEL_Pos 1U |
SCB DCCISW: Level Position
| #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) |
SCB DCCISW: Set Mask
| #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) |
SCB DCCISW: Set Mask
| #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) |
SCB DCCISW: Set Mask
| #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) |
SCB DCCISW: Set Mask
| #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) |
SCB DCCISW: Set Mask
| #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) |
SCB DCCISW: Set Mask
| #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) |
SCB DCCISW: Set Mask
| #define SCB_DCCISW_SET_Msk (0xFFUL << SCB_DCCISW_SET_Pos) |
SCB DCCISW: Set Mask
| #define SCB_DCCISW_SET_Pos 5U |
SCB DCCISW: Set Position
| #define SCB_DCCISW_SET_Pos 5U |
SCB DCCISW: Set Position
| #define SCB_DCCISW_SET_Pos 5U |
SCB DCCISW: Set Position
| #define SCB_DCCISW_SET_Pos 5U |
SCB DCCISW: Set Position
| #define SCB_DCCISW_SET_Pos 5U |
SCB DCCISW: Set Position
| #define SCB_DCCISW_SET_Pos 5U |
SCB DCCISW: Set Position
| #define SCB_DCCISW_SET_Pos 5U |
SCB DCCISW: Set Position
| #define SCB_DCCISW_SET_Pos 5U |
SCB DCCISW: Set Position
| #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) |
SCB DCCISW: Way Mask
| #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) |
SCB DCCISW: Way Mask
| #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) |
SCB DCCISW: Way Mask
| #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) |
SCB DCCISW: Way Mask
| #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) |
SCB DCCISW: Way Mask
| #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) |
SCB DCCISW: Way Mask
| #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) |
SCB DCCISW: Way Mask
| #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) |
SCB DCCISW: Way Mask
| #define SCB_DCCISW_WAY_Pos 30U |
SCB DCCISW: Way Position
| #define SCB_DCCISW_WAY_Pos 30U |
SCB DCCISW: Way Position
| #define SCB_DCCISW_WAY_Pos 30U |
SCB DCCISW: Way Position
| #define SCB_DCCISW_WAY_Pos 30U |
SCB DCCISW: Way Position
| #define SCB_DCCISW_WAY_Pos 30U |
SCB DCCISW: Way Position
| #define SCB_DCCISW_WAY_Pos 30U |
SCB DCCISW: Way Position
| #define SCB_DCCISW_WAY_Pos 30U |
SCB DCCISW: Way Position
| #define SCB_DCCISW_WAY_Pos 30U |
SCB DCCISW: Way Position
| #define SCB_DCCSW_LEVEL_Msk (7UL << SCB_DCCSW_LEVEL_Pos) |
SCB DCCSW: Level Mask
| #define SCB_DCCSW_LEVEL_Pos 1U |
SCB DCCSW: Level Position
| #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) |
SCB DCCSW: Set Mask
| #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) |
SCB DCCSW: Set Mask
| #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) |
SCB DCCSW: Set Mask
| #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) |
SCB DCCSW: Set Mask
| #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) |
SCB DCCSW: Set Mask
| #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) |
SCB DCCSW: Set Mask
| #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) |
SCB DCCSW: Set Mask
| #define SCB_DCCSW_SET_Msk (0xFFUL << SCB_DCCSW_SET_Pos) |
SCB DCCSW: Set Mask
| #define SCB_DCCSW_SET_Pos 5U |
SCB DCCSW: Set Position
| #define SCB_DCCSW_SET_Pos 5U |
SCB DCCSW: Set Position
| #define SCB_DCCSW_SET_Pos 5U |
SCB DCCSW: Set Position
| #define SCB_DCCSW_SET_Pos 5U |
SCB DCCSW: Set Position
| #define SCB_DCCSW_SET_Pos 5U |
SCB DCCSW: Set Position
| #define SCB_DCCSW_SET_Pos 5U |
SCB DCCSW: Set Position
| #define SCB_DCCSW_SET_Pos 5U |
SCB DCCSW: Set Position
| #define SCB_DCCSW_SET_Pos 5U |
SCB DCCSW: Set Position
| #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) |
SCB DCCSW: Way Mask
| #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) |
SCB DCCSW: Way Mask
| #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) |
SCB DCCSW: Way Mask
| #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) |
SCB DCCSW: Way Mask
| #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) |
SCB DCCSW: Way Mask
| #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) |
SCB DCCSW: Way Mask
| #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) |
SCB DCCSW: Way Mask
| #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) |
SCB DCCSW: Way Mask
| #define SCB_DCCSW_WAY_Pos 30U |
SCB DCCSW: Way Position
| #define SCB_DCCSW_WAY_Pos 30U |
SCB DCCSW: Way Position
| #define SCB_DCCSW_WAY_Pos 30U |
SCB DCCSW: Way Position
| #define SCB_DCCSW_WAY_Pos 30U |
SCB DCCSW: Way Position
| #define SCB_DCCSW_WAY_Pos 30U |
SCB DCCSW: Way Position
| #define SCB_DCCSW_WAY_Pos 30U |
SCB DCCSW: Way Position
| #define SCB_DCCSW_WAY_Pos 30U |
SCB DCCSW: Way Position
| #define SCB_DCCSW_WAY_Pos 30U |
SCB DCCSW: Way Position
| #define SCB_DCISW_LEVEL_Msk (7UL << SCB_DCISW_LEVEL_Pos) |
SCB DCISW: Level Mask
| #define SCB_DCISW_LEVEL_Pos 1U |
SCB DCISW: Level Position
| #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) |
SCB DCISW: Set Mask
| #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) |
SCB DCISW: Set Mask
| #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) |
SCB DCISW: Set Mask
| #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) |
SCB DCISW: Set Mask
| #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) |
SCB DCISW: Set Mask
| #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) |
SCB DCISW: Set Mask
| #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) |
SCB DCISW: Set Mask
| #define SCB_DCISW_SET_Msk (0xFFUL << SCB_DCISW_SET_Pos) |
SCB DCISW: Set Mask
| #define SCB_DCISW_SET_Pos 5U |
SCB DCISW: Set Position
| #define SCB_DCISW_SET_Pos 5U |
SCB DCISW: Set Position
| #define SCB_DCISW_SET_Pos 5U |
SCB DCISW: Set Position
| #define SCB_DCISW_SET_Pos 5U |
SCB DCISW: Set Position
| #define SCB_DCISW_SET_Pos 5U |
SCB DCISW: Set Position
| #define SCB_DCISW_SET_Pos 5U |
SCB DCISW: Set Position
| #define SCB_DCISW_SET_Pos 5U |
SCB DCISW: Set Position
| #define SCB_DCISW_SET_Pos 5U |
SCB DCISW: Set Position
| #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) |
SCB DCISW: Way Mask
| #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) |
SCB DCISW: Way Mask
| #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) |
SCB DCISW: Way Mask
| #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) |
SCB DCISW: Way Mask
| #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) |
SCB DCISW: Way Mask
| #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) |
SCB DCISW: Way Mask
| #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) |
SCB DCISW: Way Mask
| #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) |
SCB DCISW: Way Mask
| #define SCB_DCISW_WAY_Pos 30U |
SCB DCISW: Way Position
| #define SCB_DCISW_WAY_Pos 30U |
SCB DCISW: Way Position
| #define SCB_DCISW_WAY_Pos 30U |
SCB DCISW: Way Position
| #define SCB_DCISW_WAY_Pos 30U |
SCB DCISW: Way Position
| #define SCB_DCISW_WAY_Pos 30U |
SCB DCISW: Way Position
| #define SCB_DCISW_WAY_Pos 30U |
SCB DCISW: Way Position
| #define SCB_DCISW_WAY_Pos 30U |
SCB DCISW: Way Position
| #define SCB_DCISW_WAY_Pos 30U |
SCB DCISW: Way Position
| #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
SCB DFSR: BKPT Mask
| #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
SCB DFSR: BKPT Mask
| #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
SCB DFSR: BKPT Mask
| #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
SCB DFSR: BKPT Mask
| #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
SCB DFSR: BKPT Mask
| #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
SCB DFSR: BKPT Mask
| #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
SCB DFSR: BKPT Mask
| #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
SCB DFSR: BKPT Mask
| #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
SCB DFSR: BKPT Mask
| #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
SCB DFSR: BKPT Mask
| #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
SCB DFSR: BKPT Mask
| #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
SCB DFSR: BKPT Mask
| #define SCB_DFSR_BKPT_Pos 1U |
SCB DFSR: BKPT Position
| #define SCB_DFSR_BKPT_Pos 1U |
SCB DFSR: BKPT Position
| #define SCB_DFSR_BKPT_Pos 1U |
SCB DFSR: BKPT Position
| #define SCB_DFSR_BKPT_Pos 1U |
SCB DFSR: BKPT Position
| #define SCB_DFSR_BKPT_Pos 1U |
SCB DFSR: BKPT Position
| #define SCB_DFSR_BKPT_Pos 1U |
SCB DFSR: BKPT Position
| #define SCB_DFSR_BKPT_Pos 1U |
SCB DFSR: BKPT Position
| #define SCB_DFSR_BKPT_Pos 1U |
SCB DFSR: BKPT Position
| #define SCB_DFSR_BKPT_Pos 1U |
SCB DFSR: BKPT Position
| #define SCB_DFSR_BKPT_Pos 1U |
SCB DFSR: BKPT Position
| #define SCB_DFSR_BKPT_Pos 1U |
SCB DFSR: BKPT Position
| #define SCB_DFSR_BKPT_Pos 1U |
SCB DFSR: BKPT Position
| #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
SCB DFSR: DWTTRAP Mask
| #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
SCB DFSR: DWTTRAP Mask
| #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
SCB DFSR: DWTTRAP Mask
| #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
SCB DFSR: DWTTRAP Mask
| #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
SCB DFSR: DWTTRAP Mask
| #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
SCB DFSR: DWTTRAP Mask
| #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
SCB DFSR: DWTTRAP Mask
| #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
SCB DFSR: DWTTRAP Mask
| #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
SCB DFSR: DWTTRAP Mask
| #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
SCB DFSR: DWTTRAP Mask
| #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
SCB DFSR: DWTTRAP Mask
| #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
SCB DFSR: DWTTRAP Mask
| #define SCB_DFSR_DWTTRAP_Pos 2U |
SCB DFSR: DWTTRAP Position
| #define SCB_DFSR_DWTTRAP_Pos 2U |
SCB DFSR: DWTTRAP Position
| #define SCB_DFSR_DWTTRAP_Pos 2U |
SCB DFSR: DWTTRAP Position
| #define SCB_DFSR_DWTTRAP_Pos 2U |
SCB DFSR: DWTTRAP Position
| #define SCB_DFSR_DWTTRAP_Pos 2U |
SCB DFSR: DWTTRAP Position
| #define SCB_DFSR_DWTTRAP_Pos 2U |
SCB DFSR: DWTTRAP Position
| #define SCB_DFSR_DWTTRAP_Pos 2U |
SCB DFSR: DWTTRAP Position
| #define SCB_DFSR_DWTTRAP_Pos 2U |
SCB DFSR: DWTTRAP Position
| #define SCB_DFSR_DWTTRAP_Pos 2U |
SCB DFSR: DWTTRAP Position
| #define SCB_DFSR_DWTTRAP_Pos 2U |
SCB DFSR: DWTTRAP Position
| #define SCB_DFSR_DWTTRAP_Pos 2U |
SCB DFSR: DWTTRAP Position
| #define SCB_DFSR_DWTTRAP_Pos 2U |
SCB DFSR: DWTTRAP Position
| #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
SCB DFSR: EXTERNAL Mask
| #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
SCB DFSR: EXTERNAL Mask
| #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
SCB DFSR: EXTERNAL Mask
| #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
SCB DFSR: EXTERNAL Mask
| #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
SCB DFSR: EXTERNAL Mask
| #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
SCB DFSR: EXTERNAL Mask
| #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
SCB DFSR: EXTERNAL Mask
| #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
SCB DFSR: EXTERNAL Mask
| #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
SCB DFSR: EXTERNAL Mask
| #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
SCB DFSR: EXTERNAL Mask
| #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
SCB DFSR: EXTERNAL Mask
| #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
SCB DFSR: EXTERNAL Mask
| #define SCB_DFSR_EXTERNAL_Pos 4U |
SCB DFSR: EXTERNAL Position
| #define SCB_DFSR_EXTERNAL_Pos 4U |
SCB DFSR: EXTERNAL Position
| #define SCB_DFSR_EXTERNAL_Pos 4U |
SCB DFSR: EXTERNAL Position
| #define SCB_DFSR_EXTERNAL_Pos 4U |
SCB DFSR: EXTERNAL Position
| #define SCB_DFSR_EXTERNAL_Pos 4U |
SCB DFSR: EXTERNAL Position
| #define SCB_DFSR_EXTERNAL_Pos 4U |
SCB DFSR: EXTERNAL Position
| #define SCB_DFSR_EXTERNAL_Pos 4U |
SCB DFSR: EXTERNAL Position
| #define SCB_DFSR_EXTERNAL_Pos 4U |
SCB DFSR: EXTERNAL Position
| #define SCB_DFSR_EXTERNAL_Pos 4U |
SCB DFSR: EXTERNAL Position
| #define SCB_DFSR_EXTERNAL_Pos 4U |
SCB DFSR: EXTERNAL Position
| #define SCB_DFSR_EXTERNAL_Pos 4U |
SCB DFSR: EXTERNAL Position
| #define SCB_DFSR_EXTERNAL_Pos 4U |
SCB DFSR: EXTERNAL Position
| #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) |
SCB DFSR: HALTED Mask
| #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) |
SCB DFSR: HALTED Mask
| #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) |
SCB DFSR: HALTED Mask
| #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) |
SCB DFSR: HALTED Mask
| #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) |
SCB DFSR: HALTED Mask
| #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) |
SCB DFSR: HALTED Mask
| #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) |
SCB DFSR: HALTED Mask
| #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) |
SCB DFSR: HALTED Mask
| #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) |
SCB DFSR: HALTED Mask
| #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) |
SCB DFSR: HALTED Mask
| #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) |
SCB DFSR: HALTED Mask
| #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) |
SCB DFSR: HALTED Mask
| #define SCB_DFSR_HALTED_Pos 0U |
SCB DFSR: HALTED Position
| #define SCB_DFSR_HALTED_Pos 0U |
SCB DFSR: HALTED Position
| #define SCB_DFSR_HALTED_Pos 0U |
SCB DFSR: HALTED Position
| #define SCB_DFSR_HALTED_Pos 0U |
SCB DFSR: HALTED Position
| #define SCB_DFSR_HALTED_Pos 0U |
SCB DFSR: HALTED Position
| #define SCB_DFSR_HALTED_Pos 0U |
SCB DFSR: HALTED Position
| #define SCB_DFSR_HALTED_Pos 0U |
SCB DFSR: HALTED Position
| #define SCB_DFSR_HALTED_Pos 0U |
SCB DFSR: HALTED Position
| #define SCB_DFSR_HALTED_Pos 0U |
SCB DFSR: HALTED Position
| #define SCB_DFSR_HALTED_Pos 0U |
SCB DFSR: HALTED Position
| #define SCB_DFSR_HALTED_Pos 0U |
SCB DFSR: HALTED Position
| #define SCB_DFSR_HALTED_Pos 0U |
SCB DFSR: HALTED Position
| #define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) |
SCB DFSR: PMU Mask
| #define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) |
SCB DFSR: PMU Mask
| #define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) |
SCB DFSR: PMU Mask
| #define SCB_DFSR_PMU_Pos 5U |
SCB DFSR: PMU Position
| #define SCB_DFSR_PMU_Pos 5U |
SCB DFSR: PMU Position
| #define SCB_DFSR_PMU_Pos 5U |
SCB DFSR: PMU Position
| #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
SCB DFSR: VCATCH Mask
| #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
SCB DFSR: VCATCH Mask
| #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
SCB DFSR: VCATCH Mask
| #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
SCB DFSR: VCATCH Mask
| #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
SCB DFSR: VCATCH Mask
| #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
SCB DFSR: VCATCH Mask
| #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
SCB DFSR: VCATCH Mask
| #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
SCB DFSR: VCATCH Mask
| #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
SCB DFSR: VCATCH Mask
| #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
SCB DFSR: VCATCH Mask
| #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
SCB DFSR: VCATCH Mask
| #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
SCB DFSR: VCATCH Mask
| #define SCB_DFSR_VCATCH_Pos 3U |
SCB DFSR: VCATCH Position
| #define SCB_DFSR_VCATCH_Pos 3U |
SCB DFSR: VCATCH Position
| #define SCB_DFSR_VCATCH_Pos 3U |
SCB DFSR: VCATCH Position
| #define SCB_DFSR_VCATCH_Pos 3U |
SCB DFSR: VCATCH Position
| #define SCB_DFSR_VCATCH_Pos 3U |
SCB DFSR: VCATCH Position
| #define SCB_DFSR_VCATCH_Pos 3U |
SCB DFSR: VCATCH Position
| #define SCB_DFSR_VCATCH_Pos 3U |
SCB DFSR: VCATCH Position
| #define SCB_DFSR_VCATCH_Pos 3U |
SCB DFSR: VCATCH Position
| #define SCB_DFSR_VCATCH_Pos 3U |
SCB DFSR: VCATCH Position
| #define SCB_DFSR_VCATCH_Pos 3U |
SCB DFSR: VCATCH Position
| #define SCB_DFSR_VCATCH_Pos 3U |
SCB DFSR: VCATCH Position
| #define SCB_DFSR_VCATCH_Pos 3U |
SCB DFSR: VCATCH Position
| #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) |
SCB DTCMCR: EN Mask
| #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) |
SCB DTCMCR: EN Mask
| #define SCB_DTCMCR_EN_Pos 0U |
SCB DTCMCR: EN Position
| #define SCB_DTCMCR_EN_Pos 0U |
SCB DTCMCR: EN Position
| #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) |
SCB DTCMCR: RETEN Mask
| #define SCB_DTCMCR_RETEN_Pos 2U |
SCB DTCMCR: RETEN Position
| #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) |
SCB DTCMCR: RMW Mask
| #define SCB_DTCMCR_RMW_Pos 1U |
SCB DTCMCR: RMW Position
| #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) |
SCB DTCMCR: SZ Mask
| #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) |
SCB DTCMCR: SZ Mask
| #define SCB_DTCMCR_SZ_Pos 3U |
SCB DTCMCR: SZ Position
| #define SCB_DTCMCR_SZ_Pos 3U |
SCB DTCMCR: SZ Position
| #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
SCB HFSR: DEBUGEVT Mask
| #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
SCB HFSR: DEBUGEVT Mask
| #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
SCB HFSR: DEBUGEVT Mask
| #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
SCB HFSR: DEBUGEVT Mask
| #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
SCB HFSR: DEBUGEVT Mask
| #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
SCB HFSR: DEBUGEVT Mask
| #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
SCB HFSR: DEBUGEVT Mask
| #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
SCB HFSR: DEBUGEVT Mask
| #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
SCB HFSR: DEBUGEVT Mask
| #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
SCB HFSR: DEBUGEVT Mask
| #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
SCB HFSR: DEBUGEVT Mask
| #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
SCB HFSR: DEBUGEVT Mask
| #define SCB_HFSR_DEBUGEVT_Pos 31U |
SCB HFSR: DEBUGEVT Position
| #define SCB_HFSR_DEBUGEVT_Pos 31U |
SCB HFSR: DEBUGEVT Position
| #define SCB_HFSR_DEBUGEVT_Pos 31U |
SCB HFSR: DEBUGEVT Position
| #define SCB_HFSR_DEBUGEVT_Pos 31U |
SCB HFSR: DEBUGEVT Position
| #define SCB_HFSR_DEBUGEVT_Pos 31U |
SCB HFSR: DEBUGEVT Position
| #define SCB_HFSR_DEBUGEVT_Pos 31U |
SCB HFSR: DEBUGEVT Position
| #define SCB_HFSR_DEBUGEVT_Pos 31U |
SCB HFSR: DEBUGEVT Position
| #define SCB_HFSR_DEBUGEVT_Pos 31U |
SCB HFSR: DEBUGEVT Position
| #define SCB_HFSR_DEBUGEVT_Pos 31U |
SCB HFSR: DEBUGEVT Position
| #define SCB_HFSR_DEBUGEVT_Pos 31U |
SCB HFSR: DEBUGEVT Position
| #define SCB_HFSR_DEBUGEVT_Pos 31U |
SCB HFSR: DEBUGEVT Position
| #define SCB_HFSR_DEBUGEVT_Pos 31U |
SCB HFSR: DEBUGEVT Position
| #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
SCB HFSR: FORCED Mask
| #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
SCB HFSR: FORCED Mask
| #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
SCB HFSR: FORCED Mask
| #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
SCB HFSR: FORCED Mask
| #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
SCB HFSR: FORCED Mask
| #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
SCB HFSR: FORCED Mask
| #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
SCB HFSR: FORCED Mask
| #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
SCB HFSR: FORCED Mask
| #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
SCB HFSR: FORCED Mask
| #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
SCB HFSR: FORCED Mask
| #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
SCB HFSR: FORCED Mask
| #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
SCB HFSR: FORCED Mask
| #define SCB_HFSR_FORCED_Pos 30U |
SCB HFSR: FORCED Position
| #define SCB_HFSR_FORCED_Pos 30U |
SCB HFSR: FORCED Position
| #define SCB_HFSR_FORCED_Pos 30U |
SCB HFSR: FORCED Position
| #define SCB_HFSR_FORCED_Pos 30U |
SCB HFSR: FORCED Position
| #define SCB_HFSR_FORCED_Pos 30U |
SCB HFSR: FORCED Position
| #define SCB_HFSR_FORCED_Pos 30U |
SCB HFSR: FORCED Position
| #define SCB_HFSR_FORCED_Pos 30U |
SCB HFSR: FORCED Position
| #define SCB_HFSR_FORCED_Pos 30U |
SCB HFSR: FORCED Position
| #define SCB_HFSR_FORCED_Pos 30U |
SCB HFSR: FORCED Position
| #define SCB_HFSR_FORCED_Pos 30U |
SCB HFSR: FORCED Position
| #define SCB_HFSR_FORCED_Pos 30U |
SCB HFSR: FORCED Position
| #define SCB_HFSR_FORCED_Pos 30U |
SCB HFSR: FORCED Position
| #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
SCB HFSR: VECTTBL Mask
| #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
SCB HFSR: VECTTBL Mask
| #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
SCB HFSR: VECTTBL Mask
| #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
SCB HFSR: VECTTBL Mask
| #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
SCB HFSR: VECTTBL Mask
| #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
SCB HFSR: VECTTBL Mask
| #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
SCB HFSR: VECTTBL Mask
| #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
SCB HFSR: VECTTBL Mask
| #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
SCB HFSR: VECTTBL Mask
| #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
SCB HFSR: VECTTBL Mask
| #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
SCB HFSR: VECTTBL Mask
| #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
SCB HFSR: VECTTBL Mask
| #define SCB_HFSR_VECTTBL_Pos 1U |
SCB HFSR: VECTTBL Position
| #define SCB_HFSR_VECTTBL_Pos 1U |
SCB HFSR: VECTTBL Position
| #define SCB_HFSR_VECTTBL_Pos 1U |
SCB HFSR: VECTTBL Position
| #define SCB_HFSR_VECTTBL_Pos 1U |
SCB HFSR: VECTTBL Position
| #define SCB_HFSR_VECTTBL_Pos 1U |
SCB HFSR: VECTTBL Position
| #define SCB_HFSR_VECTTBL_Pos 1U |
SCB HFSR: VECTTBL Position
| #define SCB_HFSR_VECTTBL_Pos 1U |
SCB HFSR: VECTTBL Position
| #define SCB_HFSR_VECTTBL_Pos 1U |
SCB HFSR: VECTTBL Position
| #define SCB_HFSR_VECTTBL_Pos 1U |
SCB HFSR: VECTTBL Position
| #define SCB_HFSR_VECTTBL_Pos 1U |
SCB HFSR: VECTTBL Position
| #define SCB_HFSR_VECTTBL_Pos 1U |
SCB HFSR: VECTTBL Position
| #define SCB_HFSR_VECTTBL_Pos 1U |
SCB HFSR: VECTTBL Position
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
| #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk |
SCB ICSR: NMIPENDSET Mask, backward compatibility
SCB ICSR: NMIPENDSET Mask
| #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk |
SCB ICSR: NMIPENDSET Mask, backward compatibility
SCB ICSR: NMIPENDSET Mask
| #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk |
SCB ICSR: NMIPENDSET Mask, backward compatibility
SCB ICSR: NMIPENDSET Mask
| #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) |
SCB ICSR: NMIPENDSET Mask
SCB ICSR: NMIPENDSET Mask, backward compatibility
| #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) |
SCB ICSR: NMIPENDSET Mask
SCB ICSR: NMIPENDSET Mask, backward compatibility
| #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) |
SCB ICSR: NMIPENDSET Mask
SCB ICSR: NMIPENDSET Mask, backward compatibility
| #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk |
SCB ICSR: NMIPENDSET Mask, backward compatibility
SCB ICSR: NMIPENDSET Mask
| #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) |
SCB ICSR: NMIPENDSET Mask
SCB ICSR: NMIPENDSET Mask, backward compatibility
| #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk |
SCB ICSR: NMIPENDSET Mask, backward compatibility
SCB ICSR: NMIPENDSET Mask
| #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk |
SCB ICSR: NMIPENDSET Mask, backward compatibility
SCB ICSR: NMIPENDSET Mask
| #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) |
SCB ICSR: NMIPENDSET Mask
SCB ICSR: NMIPENDSET Mask, backward compatibility
| #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk |
SCB ICSR: NMIPENDSET Mask, backward compatibility
SCB ICSR: NMIPENDSET Mask
| #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) |
SCB ICSR: NMIPENDSET Mask
SCB ICSR: NMIPENDSET Mask, backward compatibility
| #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk |
SCB ICSR: NMIPENDSET Mask, backward compatibility
SCB ICSR: NMIPENDSET Mask
| #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) |
SCB ICSR: NMIPENDSET Mask
SCB ICSR: NMIPENDSET Mask, backward compatibility
| #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) |
SCB ICSR: NMIPENDSET Mask
SCB ICSR: NMIPENDSET Mask, backward compatibility
| #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk |
SCB ICSR: NMIPENDSET Mask, backward compatibility
SCB ICSR: NMIPENDSET Mask
| #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) |
SCB ICSR: NMIPENDSET Mask
| #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) |
SCB ICSR: NMIPENDSET Mask
| #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos |
SCB ICSR: NMIPENDSET Position, backward compatibility
SCB ICSR: NMIPENDSET Position
| #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos |
SCB ICSR: NMIPENDSET Position, backward compatibility
SCB ICSR: NMIPENDSET Position
| #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos |
SCB ICSR: NMIPENDSET Position, backward compatibility
SCB ICSR: NMIPENDSET Position
| #define SCB_ICSR_NMIPENDSET_Pos 31U |
SCB ICSR: NMIPENDSET Position
SCB ICSR: NMIPENDSET Position, backward compatibility
| #define SCB_ICSR_NMIPENDSET_Pos 31U |
SCB ICSR: NMIPENDSET Position
SCB ICSR: NMIPENDSET Position, backward compatibility
| #define SCB_ICSR_NMIPENDSET_Pos 31U |
SCB ICSR: NMIPENDSET Position
SCB ICSR: NMIPENDSET Position, backward compatibility
| #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos |
SCB ICSR: NMIPENDSET Position, backward compatibility
SCB ICSR: NMIPENDSET Position
| #define SCB_ICSR_NMIPENDSET_Pos 31U |
SCB ICSR: NMIPENDSET Position
SCB ICSR: NMIPENDSET Position, backward compatibility
| #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos |
SCB ICSR: NMIPENDSET Position, backward compatibility
SCB ICSR: NMIPENDSET Position
| #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos |
SCB ICSR: NMIPENDSET Position, backward compatibility
SCB ICSR: NMIPENDSET Position
| #define SCB_ICSR_NMIPENDSET_Pos 31U |
SCB ICSR: NMIPENDSET Position
SCB ICSR: NMIPENDSET Position, backward compatibility
| #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos |
SCB ICSR: NMIPENDSET Position, backward compatibility
SCB ICSR: NMIPENDSET Position
| #define SCB_ICSR_NMIPENDSET_Pos 31U |
SCB ICSR: NMIPENDSET Position
SCB ICSR: NMIPENDSET Position, backward compatibility
| #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos |
SCB ICSR: NMIPENDSET Position, backward compatibility
SCB ICSR: NMIPENDSET Position
| #define SCB_ICSR_NMIPENDSET_Pos 31U |
SCB ICSR: NMIPENDSET Position
SCB ICSR: NMIPENDSET Position, backward compatibility
| #define SCB_ICSR_NMIPENDSET_Pos 31U |
SCB ICSR: NMIPENDSET Position
SCB ICSR: NMIPENDSET Position, backward compatibility
| #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos |
SCB ICSR: NMIPENDSET Position, backward compatibility
SCB ICSR: NMIPENDSET Position
| #define SCB_ICSR_NMIPENDSET_Pos 31U |
SCB ICSR: NMIPENDSET Position
| #define SCB_ICSR_NMIPENDSET_Pos 31U |
SCB ICSR: NMIPENDSET Position
| #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) |
SCB ICSR: PENDNMICLR Mask
| #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) |
SCB ICSR: PENDNMICLR Mask
| #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) |
SCB ICSR: PENDNMICLR Mask
| #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) |
SCB ICSR: PENDNMICLR Mask
| #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) |
SCB ICSR: PENDNMICLR Mask
| #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) |
SCB ICSR: PENDNMICLR Mask
| #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) |
SCB ICSR: PENDNMICLR Mask
| #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) |
SCB ICSR: PENDNMICLR Mask
| #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) |
SCB ICSR: PENDNMICLR Mask
| #define SCB_ICSR_PENDNMICLR_Pos 30U |
SCB ICSR: PENDNMICLR Position
| #define SCB_ICSR_PENDNMICLR_Pos 30U |
SCB ICSR: PENDNMICLR Position
| #define SCB_ICSR_PENDNMICLR_Pos 30U |
SCB ICSR: PENDNMICLR Position
| #define SCB_ICSR_PENDNMICLR_Pos 30U |
SCB ICSR: PENDNMICLR Position
| #define SCB_ICSR_PENDNMICLR_Pos 30U |
SCB ICSR: PENDNMICLR Position
| #define SCB_ICSR_PENDNMICLR_Pos 30U |
SCB ICSR: PENDNMICLR Position
| #define SCB_ICSR_PENDNMICLR_Pos 30U |
SCB ICSR: PENDNMICLR Position
| #define SCB_ICSR_PENDNMICLR_Pos 30U |
SCB ICSR: PENDNMICLR Position
| #define SCB_ICSR_PENDNMICLR_Pos 30U |
SCB ICSR: PENDNMICLR Position
| #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) |
SCB ICSR: PENDNMISET Mask
| #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) |
SCB ICSR: PENDNMISET Mask
| #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) |
SCB ICSR: PENDNMISET Mask
| #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) |
SCB ICSR: PENDNMISET Mask
| #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) |
SCB ICSR: PENDNMISET Mask
| #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) |
SCB ICSR: PENDNMISET Mask
| #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) |
SCB ICSR: PENDNMISET Mask
| #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) |
SCB ICSR: PENDNMISET Mask
| #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) |
SCB ICSR: PENDNMISET Mask
| #define SCB_ICSR_PENDNMISET_Pos 31U |
SCB ICSR: PENDNMISET Position
| #define SCB_ICSR_PENDNMISET_Pos 31U |
SCB ICSR: PENDNMISET Position
| #define SCB_ICSR_PENDNMISET_Pos 31U |
SCB ICSR: PENDNMISET Position
| #define SCB_ICSR_PENDNMISET_Pos 31U |
SCB ICSR: PENDNMISET Position
| #define SCB_ICSR_PENDNMISET_Pos 31U |
SCB ICSR: PENDNMISET Position
| #define SCB_ICSR_PENDNMISET_Pos 31U |
SCB ICSR: PENDNMISET Position
| #define SCB_ICSR_PENDNMISET_Pos 31U |
SCB ICSR: PENDNMISET Position
| #define SCB_ICSR_PENDNMISET_Pos 31U |
SCB ICSR: PENDNMISET Position
| #define SCB_ICSR_PENDNMISET_Pos 31U |
SCB ICSR: PENDNMISET Position
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
| #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
SCB ICSR: RETTOBASE Mask
| #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
SCB ICSR: RETTOBASE Mask
| #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
SCB ICSR: RETTOBASE Mask
| #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
SCB ICSR: RETTOBASE Mask
| #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
SCB ICSR: RETTOBASE Mask
| #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
SCB ICSR: RETTOBASE Mask
| #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
SCB ICSR: RETTOBASE Mask
| #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
SCB ICSR: RETTOBASE Mask
| #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
SCB ICSR: RETTOBASE Mask
| #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
SCB ICSR: RETTOBASE Mask
| #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
SCB ICSR: RETTOBASE Mask
| #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
SCB ICSR: RETTOBASE Mask
| #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
SCB ICSR: RETTOBASE Mask
| #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
SCB ICSR: RETTOBASE Mask
| #define SCB_ICSR_RETTOBASE_Pos 11U |
SCB ICSR: RETTOBASE Position
| #define SCB_ICSR_RETTOBASE_Pos 11U |
SCB ICSR: RETTOBASE Position
| #define SCB_ICSR_RETTOBASE_Pos 11U |
SCB ICSR: RETTOBASE Position
| #define SCB_ICSR_RETTOBASE_Pos 11U |
SCB ICSR: RETTOBASE Position
| #define SCB_ICSR_RETTOBASE_Pos 11U |
SCB ICSR: RETTOBASE Position
| #define SCB_ICSR_RETTOBASE_Pos 11U |
SCB ICSR: RETTOBASE Position
| #define SCB_ICSR_RETTOBASE_Pos 11U |
SCB ICSR: RETTOBASE Position
| #define SCB_ICSR_RETTOBASE_Pos 11U |
SCB ICSR: RETTOBASE Position
| #define SCB_ICSR_RETTOBASE_Pos 11U |
SCB ICSR: RETTOBASE Position
| #define SCB_ICSR_RETTOBASE_Pos 11U |
SCB ICSR: RETTOBASE Position
| #define SCB_ICSR_RETTOBASE_Pos 11U |
SCB ICSR: RETTOBASE Position
| #define SCB_ICSR_RETTOBASE_Pos 11U |
SCB ICSR: RETTOBASE Position
| #define SCB_ICSR_RETTOBASE_Pos 11U |
SCB ICSR: RETTOBASE Position
| #define SCB_ICSR_RETTOBASE_Pos 11U |
SCB ICSR: RETTOBASE Position
| #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) |
SCB ICSR: STTNS Mask (Security Extension)
| #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) |
SCB ICSR: STTNS Mask (Security Extension)
| #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) |
SCB ICSR: STTNS Mask (Security Extension)
| #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) |
SCB ICSR: STTNS Mask (Security Extension)
| #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) |
SCB ICSR: STTNS Mask (Security Extension)
| #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) |
SCB ICSR: STTNS Mask (Security Extension)
| #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) |
SCB ICSR: STTNS Mask (Security Extension)
| #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) |
SCB ICSR: STTNS Mask (Security Extension)
| #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) |
SCB ICSR: STTNS Mask (Security Extension)
| #define SCB_ICSR_STTNS_Pos 24U |
SCB ICSR: STTNS Position (Security Extension)
| #define SCB_ICSR_STTNS_Pos 24U |
SCB ICSR: STTNS Position (Security Extension)
| #define SCB_ICSR_STTNS_Pos 24U |
SCB ICSR: STTNS Position (Security Extension)
| #define SCB_ICSR_STTNS_Pos 24U |
SCB ICSR: STTNS Position (Security Extension)
| #define SCB_ICSR_STTNS_Pos 24U |
SCB ICSR: STTNS Position (Security Extension)
| #define SCB_ICSR_STTNS_Pos 24U |
SCB ICSR: STTNS Position (Security Extension)
| #define SCB_ICSR_STTNS_Pos 24U |
SCB ICSR: STTNS Position (Security Extension)
| #define SCB_ICSR_STTNS_Pos 24U |
SCB ICSR: STTNS Position (Security Extension)
| #define SCB_ICSR_STTNS_Pos 24U |
SCB ICSR: STTNS Position (Security Extension)
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
| #define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) |
SCB ID_DFR: MProfDbg Mask
| #define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) |
SCB ID_DFR: MProfDbg Mask
| #define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) |
SCB ID_DFR: MProfDbg Mask
| #define SCB_ID_DFR_MProfDbg_Pos 20U |
SCB ID_DFR: MProfDbg Position
| #define SCB_ID_DFR_MProfDbg_Pos 20U |
SCB ID_DFR: MProfDbg Position
| #define SCB_ID_DFR_MProfDbg_Pos 20U |
SCB ID_DFR: MProfDbg Position
| #define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) |
SCB ID_DFR: UDE Mask
| #define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) |
SCB ID_DFR: UDE Mask
| #define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) |
SCB ID_DFR: UDE Mask
| #define SCB_ID_DFR_UDE_Pos 28U |
SCB ID_DFR: UDE Position
| #define SCB_ID_DFR_UDE_Pos 28U |
SCB ID_DFR: UDE Position
| #define SCB_ID_DFR_UDE_Pos 28U |
SCB ID_DFR: UDE Position
| #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) |
SCB ITCMCR: EN Mask
| #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) |
SCB ITCMCR: EN Mask
| #define SCB_ITCMCR_EN_Pos 0U |
SCB ITCMCR: EN Position
| #define SCB_ITCMCR_EN_Pos 0U |
SCB ITCMCR: EN Position
| #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) |
SCB ITCMCR: RETEN Mask
| #define SCB_ITCMCR_RETEN_Pos 2U |
SCB ITCMCR: RETEN Position
| #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) |
SCB ITCMCR: RMW Mask
| #define SCB_ITCMCR_RMW_Pos 1U |
SCB ITCMCR: RMW Position
| #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) |
SCB ITCMCR: SZ Mask
| #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) |
SCB ITCMCR: SZ Mask
| #define SCB_ITCMCR_SZ_Pos 3U |
SCB ITCMCR: SZ Position
| #define SCB_ITCMCR_SZ_Pos 3U |
SCB ITCMCR: SZ Position
| #define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) |
SCB NSACR: CP0 Mask
| #define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) |
SCB NSACR: CP0 Mask
| #define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) |
SCB NSACR: CP0 Mask
| #define SCB_NSACR_CP0_Pos 0U |
SCB NSACR: CP0 Position
| #define SCB_NSACR_CP0_Pos 0U |
SCB NSACR: CP0 Position
| #define SCB_NSACR_CP0_Pos 0U |
SCB NSACR: CP0 Position
| #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) |
SCB NSACR: CP10 Mask
| #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) |
SCB NSACR: CP10 Mask
| #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) |
SCB NSACR: CP10 Mask
| #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) |
SCB NSACR: CP10 Mask
| #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) |
SCB NSACR: CP10 Mask
| #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) |
SCB NSACR: CP10 Mask
| #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) |
SCB NSACR: CP10 Mask
| #define SCB_NSACR_CP10_Pos 10U |
SCB NSACR: CP10 Position
| #define SCB_NSACR_CP10_Pos 10U |
SCB NSACR: CP10 Position
| #define SCB_NSACR_CP10_Pos 10U |
SCB NSACR: CP10 Position
| #define SCB_NSACR_CP10_Pos 10U |
SCB NSACR: CP10 Position
| #define SCB_NSACR_CP10_Pos 10U |
SCB NSACR: CP10 Position
| #define SCB_NSACR_CP10_Pos 10U |
SCB NSACR: CP10 Position
| #define SCB_NSACR_CP10_Pos 10U |
SCB NSACR: CP10 Position
| #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) |
SCB NSACR: CP11 Mask
| #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) |
SCB NSACR: CP11 Mask
| #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) |
SCB NSACR: CP11 Mask
| #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) |
SCB NSACR: CP11 Mask
| #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) |
SCB NSACR: CP11 Mask
| #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) |
SCB NSACR: CP11 Mask
| #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) |
SCB NSACR: CP11 Mask
| #define SCB_NSACR_CP11_Pos 11U |
SCB NSACR: CP11 Position
| #define SCB_NSACR_CP11_Pos 11U |
SCB NSACR: CP11 Position
| #define SCB_NSACR_CP11_Pos 11U |
SCB NSACR: CP11 Position
| #define SCB_NSACR_CP11_Pos 11U |
SCB NSACR: CP11 Position
| #define SCB_NSACR_CP11_Pos 11U |
SCB NSACR: CP11 Position
| #define SCB_NSACR_CP11_Pos 11U |
SCB NSACR: CP11 Position
| #define SCB_NSACR_CP11_Pos 11U |
SCB NSACR: CP11 Position
| #define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) |
SCB NSACR: CP1 Mask
| #define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) |
SCB NSACR: CP1 Mask
| #define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) |
SCB NSACR: CP1 Mask
| #define SCB_NSACR_CP1_Pos 1U |
SCB NSACR: CP1 Position
| #define SCB_NSACR_CP1_Pos 1U |
SCB NSACR: CP1 Position
| #define SCB_NSACR_CP1_Pos 1U |
SCB NSACR: CP1 Position
| #define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) |
SCB NSACR: CP2 Mask
| #define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) |
SCB NSACR: CP2 Mask
| #define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) |
SCB NSACR: CP2 Mask
| #define SCB_NSACR_CP2_Pos 2U |
SCB NSACR: CP2 Position
| #define SCB_NSACR_CP2_Pos 2U |
SCB NSACR: CP2 Position
| #define SCB_NSACR_CP2_Pos 2U |
SCB NSACR: CP2 Position
| #define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) |
SCB NSACR: CP3 Mask
| #define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) |
SCB NSACR: CP3 Mask
| #define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) |
SCB NSACR: CP3 Mask
| #define SCB_NSACR_CP3_Pos 3U |
SCB NSACR: CP3 Position
| #define SCB_NSACR_CP3_Pos 3U |
SCB NSACR: CP3 Position
| #define SCB_NSACR_CP3_Pos 3U |
SCB NSACR: CP3 Position
| #define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) |
SCB NSACR: CP4 Mask
| #define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) |
SCB NSACR: CP4 Mask
| #define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) |
SCB NSACR: CP4 Mask
| #define SCB_NSACR_CP4_Pos 4U |
SCB NSACR: CP4 Position
| #define SCB_NSACR_CP4_Pos 4U |
SCB NSACR: CP4 Position
| #define SCB_NSACR_CP4_Pos 4U |
SCB NSACR: CP4 Position
| #define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) |
SCB NSACR: CP5 Mask
| #define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) |
SCB NSACR: CP5 Mask
| #define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) |
SCB NSACR: CP5 Mask
| #define SCB_NSACR_CP5_Pos 5U |
SCB NSACR: CP5 Position
| #define SCB_NSACR_CP5_Pos 5U |
SCB NSACR: CP5 Position
| #define SCB_NSACR_CP5_Pos 5U |
SCB NSACR: CP5 Position
| #define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) |
SCB NSACR: CP6 Mask
| #define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) |
SCB NSACR: CP6 Mask
| #define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) |
SCB NSACR: CP6 Mask
| #define SCB_NSACR_CP6_Pos 6U |
SCB NSACR: CP6 Position
| #define SCB_NSACR_CP6_Pos 6U |
SCB NSACR: CP6 Position
| #define SCB_NSACR_CP6_Pos 6U |
SCB NSACR: CP6 Position
| #define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) |
SCB NSACR: CP7 Mask
| #define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) |
SCB NSACR: CP7 Mask
| #define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) |
SCB NSACR: CP7 Mask
| #define SCB_NSACR_CP7_Pos 7U |
SCB NSACR: CP7 Position
| #define SCB_NSACR_CP7_Pos 7U |
SCB NSACR: CP7 Position
| #define SCB_NSACR_CP7_Pos 7U |
SCB NSACR: CP7 Position
| #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) |
SCB NSACR: CPn Mask
| #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) |
SCB NSACR: CPn Mask
| #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) |
SCB NSACR: CPn Mask
| #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) |
SCB NSACR: CPn Mask
| #define SCB_NSACR_CPn_Pos 0U |
SCB NSACR: CPn Position
| #define SCB_NSACR_CPn_Pos 0U |
SCB NSACR: CPn Position
| #define SCB_NSACR_CPn_Pos 0U |
SCB NSACR: CPn Position
| #define SCB_NSACR_CPn_Pos 0U |
SCB NSACR: CPn Position
| #define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) |
SCB RFSR: IS Mask
| #define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) |
SCB RFSR: IS Mask
| #define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) |
SCB RFSR: IS Mask
| #define SCB_RFSR_IS_Pos 16U |
SCB RFSR: IS Position
| #define SCB_RFSR_IS_Pos 16U |
SCB RFSR: IS Position
| #define SCB_RFSR_IS_Pos 16U |
SCB RFSR: IS Position
| #define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) |
SCB RFSR: UET Mask
| #define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) |
SCB RFSR: UET Mask
| #define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) |
SCB RFSR: UET Mask
| #define SCB_RFSR_UET_Pos 0U |
SCB RFSR: UET Position
| #define SCB_RFSR_UET_Pos 0U |
SCB RFSR: UET Position
| #define SCB_RFSR_UET_Pos 0U |
SCB RFSR: UET Position
| #define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) |
SCB RFSR: V Mask
| #define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) |
SCB RFSR: V Mask
| #define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) |
SCB RFSR: V Mask
| #define SCB_RFSR_V_Pos 31U |
SCB RFSR: V Position
| #define SCB_RFSR_V_Pos 31U |
SCB RFSR: V Position
| #define SCB_RFSR_V_Pos 31U |
SCB RFSR: V Position
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
| #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) |
SCB SCR: SLEEPDEEPS Mask
| #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) |
SCB SCR: SLEEPDEEPS Mask
| #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) |
SCB SCR: SLEEPDEEPS Mask
| #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) |
SCB SCR: SLEEPDEEPS Mask
| #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) |
SCB SCR: SLEEPDEEPS Mask
| #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) |
SCB SCR: SLEEPDEEPS Mask
| #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) |
SCB SCR: SLEEPDEEPS Mask
| #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) |
SCB SCR: SLEEPDEEPS Mask
| #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) |
SCB SCR: SLEEPDEEPS Mask
| #define SCB_SCR_SLEEPDEEPS_Pos 3U |
SCB SCR: SLEEPDEEPS Position
| #define SCB_SCR_SLEEPDEEPS_Pos 3U |
SCB SCR: SLEEPDEEPS Position
| #define SCB_SCR_SLEEPDEEPS_Pos 3U |
SCB SCR: SLEEPDEEPS Position
| #define SCB_SCR_SLEEPDEEPS_Pos 3U |
SCB SCR: SLEEPDEEPS Position
| #define SCB_SCR_SLEEPDEEPS_Pos 3U |
SCB SCR: SLEEPDEEPS Position
| #define SCB_SCR_SLEEPDEEPS_Pos 3U |
SCB SCR: SLEEPDEEPS Position
| #define SCB_SCR_SLEEPDEEPS_Pos 3U |
SCB SCR: SLEEPDEEPS Position
| #define SCB_SCR_SLEEPDEEPS_Pos 3U |
SCB SCR: SLEEPDEEPS Position
| #define SCB_SCR_SLEEPDEEPS_Pos 3U |
SCB SCR: SLEEPDEEPS Position
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
| #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
SCB SHCSR: BUSFAULTACT Mask
| #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
SCB SHCSR: BUSFAULTACT Mask
| #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
SCB SHCSR: BUSFAULTACT Mask
| #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
SCB SHCSR: BUSFAULTACT Mask
| #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
SCB SHCSR: BUSFAULTACT Mask
| #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
SCB SHCSR: BUSFAULTACT Mask
| #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
SCB SHCSR: BUSFAULTACT Mask
| #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
SCB SHCSR: BUSFAULTACT Mask
| #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
SCB SHCSR: BUSFAULTACT Mask
| #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
SCB SHCSR: BUSFAULTACT Mask
| #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
SCB SHCSR: BUSFAULTACT Mask
| #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
SCB SHCSR: BUSFAULTACT Mask
| #define SCB_SHCSR_BUSFAULTACT_Pos 1U |
SCB SHCSR: BUSFAULTACT Position
| #define SCB_SHCSR_BUSFAULTACT_Pos 1U |
SCB SHCSR: BUSFAULTACT Position
| #define SCB_SHCSR_BUSFAULTACT_Pos 1U |
SCB SHCSR: BUSFAULTACT Position
| #define SCB_SHCSR_BUSFAULTACT_Pos 1U |
SCB SHCSR: BUSFAULTACT Position
| #define SCB_SHCSR_BUSFAULTACT_Pos 1U |
SCB SHCSR: BUSFAULTACT Position
| #define SCB_SHCSR_BUSFAULTACT_Pos 1U |
SCB SHCSR: BUSFAULTACT Position
| #define SCB_SHCSR_BUSFAULTACT_Pos 1U |
SCB SHCSR: BUSFAULTACT Position
| #define SCB_SHCSR_BUSFAULTACT_Pos 1U |
SCB SHCSR: BUSFAULTACT Position
| #define SCB_SHCSR_BUSFAULTACT_Pos 1U |
SCB SHCSR: BUSFAULTACT Position
| #define SCB_SHCSR_BUSFAULTACT_Pos 1U |
SCB SHCSR: BUSFAULTACT Position
| #define SCB_SHCSR_BUSFAULTACT_Pos 1U |
SCB SHCSR: BUSFAULTACT Position
| #define SCB_SHCSR_BUSFAULTACT_Pos 1U |
SCB SHCSR: BUSFAULTACT Position
| #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
SCB SHCSR: BUSFAULTENA Mask
| #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
SCB SHCSR: BUSFAULTENA Mask
| #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
SCB SHCSR: BUSFAULTENA Mask
| #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
SCB SHCSR: BUSFAULTENA Mask
| #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
SCB SHCSR: BUSFAULTENA Mask
| #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
SCB SHCSR: BUSFAULTENA Mask
| #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
SCB SHCSR: BUSFAULTENA Mask
| #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
SCB SHCSR: BUSFAULTENA Mask
| #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
SCB SHCSR: BUSFAULTENA Mask
| #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
SCB SHCSR: BUSFAULTENA Mask
| #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
SCB SHCSR: BUSFAULTENA Mask
| #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
SCB SHCSR: BUSFAULTENA Mask
| #define SCB_SHCSR_BUSFAULTENA_Pos 17U |
SCB SHCSR: BUSFAULTENA Position
| #define SCB_SHCSR_BUSFAULTENA_Pos 17U |
SCB SHCSR: BUSFAULTENA Position
| #define SCB_SHCSR_BUSFAULTENA_Pos 17U |
SCB SHCSR: BUSFAULTENA Position
| #define SCB_SHCSR_BUSFAULTENA_Pos 17U |
SCB SHCSR: BUSFAULTENA Position
| #define SCB_SHCSR_BUSFAULTENA_Pos 17U |
SCB SHCSR: BUSFAULTENA Position
| #define SCB_SHCSR_BUSFAULTENA_Pos 17U |
SCB SHCSR: BUSFAULTENA Position
| #define SCB_SHCSR_BUSFAULTENA_Pos 17U |
SCB SHCSR: BUSFAULTENA Position
| #define SCB_SHCSR_BUSFAULTENA_Pos 17U |
SCB SHCSR: BUSFAULTENA Position
| #define SCB_SHCSR_BUSFAULTENA_Pos 17U |
SCB SHCSR: BUSFAULTENA Position
| #define SCB_SHCSR_BUSFAULTENA_Pos 17U |
SCB SHCSR: BUSFAULTENA Position
| #define SCB_SHCSR_BUSFAULTENA_Pos 17U |
SCB SHCSR: BUSFAULTENA Position
| #define SCB_SHCSR_BUSFAULTENA_Pos 17U |
SCB SHCSR: BUSFAULTENA Position
| #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
SCB SHCSR: BUSFAULTPENDED Mask
| #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
SCB SHCSR: BUSFAULTPENDED Mask
| #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
SCB SHCSR: BUSFAULTPENDED Mask
| #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
SCB SHCSR: BUSFAULTPENDED Mask
| #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
SCB SHCSR: BUSFAULTPENDED Mask
| #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
SCB SHCSR: BUSFAULTPENDED Mask
| #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
SCB SHCSR: BUSFAULTPENDED Mask
| #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
SCB SHCSR: BUSFAULTPENDED Mask
| #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
SCB SHCSR: BUSFAULTPENDED Mask
| #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
SCB SHCSR: BUSFAULTPENDED Mask
| #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
SCB SHCSR: BUSFAULTPENDED Mask
| #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
SCB SHCSR: BUSFAULTPENDED Mask
| #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U |
SCB SHCSR: BUSFAULTPENDED Position
| #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U |
SCB SHCSR: BUSFAULTPENDED Position
| #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U |
SCB SHCSR: BUSFAULTPENDED Position
| #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U |
SCB SHCSR: BUSFAULTPENDED Position
| #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U |
SCB SHCSR: BUSFAULTPENDED Position
| #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U |
SCB SHCSR: BUSFAULTPENDED Position
| #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U |
SCB SHCSR: BUSFAULTPENDED Position
| #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U |
SCB SHCSR: BUSFAULTPENDED Position
| #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U |
SCB SHCSR: BUSFAULTPENDED Position
| #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U |
SCB SHCSR: BUSFAULTPENDED Position
| #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U |
SCB SHCSR: BUSFAULTPENDED Position
| #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U |
SCB SHCSR: BUSFAULTPENDED Position
| #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) |
SCB SHCSR: HARDFAULTACT Mask
| #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) |
SCB SHCSR: HARDFAULTACT Mask
| #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) |
SCB SHCSR: HARDFAULTACT Mask
| #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) |
SCB SHCSR: HARDFAULTACT Mask
| #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) |
SCB SHCSR: HARDFAULTACT Mask
| #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) |
SCB SHCSR: HARDFAULTACT Mask
| #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) |
SCB SHCSR: HARDFAULTACT Mask
| #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) |
SCB SHCSR: HARDFAULTACT Mask
| #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) |
SCB SHCSR: HARDFAULTACT Mask
| #define SCB_SHCSR_HARDFAULTACT_Pos 2U |
SCB SHCSR: HARDFAULTACT Position
| #define SCB_SHCSR_HARDFAULTACT_Pos 2U |
SCB SHCSR: HARDFAULTACT Position
| #define SCB_SHCSR_HARDFAULTACT_Pos 2U |
SCB SHCSR: HARDFAULTACT Position
| #define SCB_SHCSR_HARDFAULTACT_Pos 2U |
SCB SHCSR: HARDFAULTACT Position
| #define SCB_SHCSR_HARDFAULTACT_Pos 2U |
SCB SHCSR: HARDFAULTACT Position
| #define SCB_SHCSR_HARDFAULTACT_Pos 2U |
SCB SHCSR: HARDFAULTACT Position
| #define SCB_SHCSR_HARDFAULTACT_Pos 2U |
SCB SHCSR: HARDFAULTACT Position
| #define SCB_SHCSR_HARDFAULTACT_Pos 2U |
SCB SHCSR: HARDFAULTACT Position
| #define SCB_SHCSR_HARDFAULTACT_Pos 2U |
SCB SHCSR: HARDFAULTACT Position
| #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) |
SCB SHCSR: HARDFAULTPENDED Mask
| #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) |
SCB SHCSR: HARDFAULTPENDED Mask
| #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) |
SCB SHCSR: HARDFAULTPENDED Mask
| #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) |
SCB SHCSR: HARDFAULTPENDED Mask
| #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) |
SCB SHCSR: HARDFAULTPENDED Mask
| #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) |
SCB SHCSR: HARDFAULTPENDED Mask
| #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) |
SCB SHCSR: HARDFAULTPENDED Mask
| #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) |
SCB SHCSR: HARDFAULTPENDED Mask
| #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) |
SCB SHCSR: HARDFAULTPENDED Mask
| #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U |
SCB SHCSR: HARDFAULTPENDED Position
| #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U |
SCB SHCSR: HARDFAULTPENDED Position
| #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U |
SCB SHCSR: HARDFAULTPENDED Position
| #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U |
SCB SHCSR: HARDFAULTPENDED Position
| #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U |
SCB SHCSR: HARDFAULTPENDED Position
| #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U |
SCB SHCSR: HARDFAULTPENDED Position
| #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U |
SCB SHCSR: HARDFAULTPENDED Position
| #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U |
SCB SHCSR: HARDFAULTPENDED Position
| #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U |
SCB SHCSR: HARDFAULTPENDED Position
| #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) |
SCB SHCSR: MEMFAULTACT Mask
| #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) |
SCB SHCSR: MEMFAULTACT Mask
| #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) |
SCB SHCSR: MEMFAULTACT Mask
| #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) |
SCB SHCSR: MEMFAULTACT Mask
| #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) |
SCB SHCSR: MEMFAULTACT Mask
| #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) |
SCB SHCSR: MEMFAULTACT Mask
| #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) |
SCB SHCSR: MEMFAULTACT Mask
| #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) |
SCB SHCSR: MEMFAULTACT Mask
| #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) |
SCB SHCSR: MEMFAULTACT Mask
| #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) |
SCB SHCSR: MEMFAULTACT Mask
| #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) |
SCB SHCSR: MEMFAULTACT Mask
| #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) |
SCB SHCSR: MEMFAULTACT Mask
| #define SCB_SHCSR_MEMFAULTACT_Pos 0U |
SCB SHCSR: MEMFAULTACT Position
| #define SCB_SHCSR_MEMFAULTACT_Pos 0U |
SCB SHCSR: MEMFAULTACT Position
| #define SCB_SHCSR_MEMFAULTACT_Pos 0U |
SCB SHCSR: MEMFAULTACT Position
| #define SCB_SHCSR_MEMFAULTACT_Pos 0U |
SCB SHCSR: MEMFAULTACT Position
| #define SCB_SHCSR_MEMFAULTACT_Pos 0U |
SCB SHCSR: MEMFAULTACT Position
| #define SCB_SHCSR_MEMFAULTACT_Pos 0U |
SCB SHCSR: MEMFAULTACT Position
| #define SCB_SHCSR_MEMFAULTACT_Pos 0U |
SCB SHCSR: MEMFAULTACT Position
| #define SCB_SHCSR_MEMFAULTACT_Pos 0U |
SCB SHCSR: MEMFAULTACT Position
| #define SCB_SHCSR_MEMFAULTACT_Pos 0U |
SCB SHCSR: MEMFAULTACT Position
| #define SCB_SHCSR_MEMFAULTACT_Pos 0U |
SCB SHCSR: MEMFAULTACT Position
| #define SCB_SHCSR_MEMFAULTACT_Pos 0U |
SCB SHCSR: MEMFAULTACT Position
| #define SCB_SHCSR_MEMFAULTACT_Pos 0U |
SCB SHCSR: MEMFAULTACT Position
| #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
SCB SHCSR: MEMFAULTENA Mask
| #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
SCB SHCSR: MEMFAULTENA Mask
| #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
SCB SHCSR: MEMFAULTENA Mask
| #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
SCB SHCSR: MEMFAULTENA Mask
| #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
SCB SHCSR: MEMFAULTENA Mask
| #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
SCB SHCSR: MEMFAULTENA Mask
| #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
SCB SHCSR: MEMFAULTENA Mask
| #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
SCB SHCSR: MEMFAULTENA Mask
| #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
SCB SHCSR: MEMFAULTENA Mask
| #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
SCB SHCSR: MEMFAULTENA Mask
| #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
SCB SHCSR: MEMFAULTENA Mask
| #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
SCB SHCSR: MEMFAULTENA Mask
| #define SCB_SHCSR_MEMFAULTENA_Pos 16U |
SCB SHCSR: MEMFAULTENA Position
| #define SCB_SHCSR_MEMFAULTENA_Pos 16U |
SCB SHCSR: MEMFAULTENA Position
| #define SCB_SHCSR_MEMFAULTENA_Pos 16U |
SCB SHCSR: MEMFAULTENA Position
| #define SCB_SHCSR_MEMFAULTENA_Pos 16U |
SCB SHCSR: MEMFAULTENA Position
| #define SCB_SHCSR_MEMFAULTENA_Pos 16U |
SCB SHCSR: MEMFAULTENA Position
| #define SCB_SHCSR_MEMFAULTENA_Pos 16U |
SCB SHCSR: MEMFAULTENA Position
| #define SCB_SHCSR_MEMFAULTENA_Pos 16U |
SCB SHCSR: MEMFAULTENA Position
| #define SCB_SHCSR_MEMFAULTENA_Pos 16U |
SCB SHCSR: MEMFAULTENA Position
| #define SCB_SHCSR_MEMFAULTENA_Pos 16U |
SCB SHCSR: MEMFAULTENA Position
| #define SCB_SHCSR_MEMFAULTENA_Pos 16U |
SCB SHCSR: MEMFAULTENA Position
| #define SCB_SHCSR_MEMFAULTENA_Pos 16U |
SCB SHCSR: MEMFAULTENA Position
| #define SCB_SHCSR_MEMFAULTENA_Pos 16U |
SCB SHCSR: MEMFAULTENA Position
| #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
SCB SHCSR: MEMFAULTPENDED Mask
| #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
SCB SHCSR: MEMFAULTPENDED Mask
| #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
SCB SHCSR: MEMFAULTPENDED Mask
| #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
SCB SHCSR: MEMFAULTPENDED Mask
| #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
SCB SHCSR: MEMFAULTPENDED Mask
| #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
SCB SHCSR: MEMFAULTPENDED Mask
| #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
SCB SHCSR: MEMFAULTPENDED Mask
| #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
SCB SHCSR: MEMFAULTPENDED Mask
| #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
SCB SHCSR: MEMFAULTPENDED Mask
| #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
SCB SHCSR: MEMFAULTPENDED Mask
| #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
SCB SHCSR: MEMFAULTPENDED Mask
| #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
SCB SHCSR: MEMFAULTPENDED Mask
| #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U |
SCB SHCSR: MEMFAULTPENDED Position
| #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U |
SCB SHCSR: MEMFAULTPENDED Position
| #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U |
SCB SHCSR: MEMFAULTPENDED Position
| #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U |
SCB SHCSR: MEMFAULTPENDED Position
| #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U |
SCB SHCSR: MEMFAULTPENDED Position
| #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U |
SCB SHCSR: MEMFAULTPENDED Position
| #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U |
SCB SHCSR: MEMFAULTPENDED Position
| #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U |
SCB SHCSR: MEMFAULTPENDED Position
| #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U |
SCB SHCSR: MEMFAULTPENDED Position
| #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U |
SCB SHCSR: MEMFAULTPENDED Position
| #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U |
SCB SHCSR: MEMFAULTPENDED Position
| #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U |
SCB SHCSR: MEMFAULTPENDED Position
| #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
SCB SHCSR: MONITORACT Mask
| #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
SCB SHCSR: MONITORACT Mask
| #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
SCB SHCSR: MONITORACT Mask
| #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
SCB SHCSR: MONITORACT Mask
| #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
SCB SHCSR: MONITORACT Mask
| #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
SCB SHCSR: MONITORACT Mask
| #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
SCB SHCSR: MONITORACT Mask
| #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
SCB SHCSR: MONITORACT Mask
| #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
SCB SHCSR: MONITORACT Mask
| #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
SCB SHCSR: MONITORACT Mask
| #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
SCB SHCSR: MONITORACT Mask
| #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
SCB SHCSR: MONITORACT Mask
| #define SCB_SHCSR_MONITORACT_Pos 8U |
SCB SHCSR: MONITORACT Position
| #define SCB_SHCSR_MONITORACT_Pos 8U |
SCB SHCSR: MONITORACT Position
| #define SCB_SHCSR_MONITORACT_Pos 8U |
SCB SHCSR: MONITORACT Position
| #define SCB_SHCSR_MONITORACT_Pos 8U |
SCB SHCSR: MONITORACT Position
| #define SCB_SHCSR_MONITORACT_Pos 8U |
SCB SHCSR: MONITORACT Position
| #define SCB_SHCSR_MONITORACT_Pos 8U |
SCB SHCSR: MONITORACT Position
| #define SCB_SHCSR_MONITORACT_Pos 8U |
SCB SHCSR: MONITORACT Position
| #define SCB_SHCSR_MONITORACT_Pos 8U |
SCB SHCSR: MONITORACT Position
| #define SCB_SHCSR_MONITORACT_Pos 8U |
SCB SHCSR: MONITORACT Position
| #define SCB_SHCSR_MONITORACT_Pos 8U |
SCB SHCSR: MONITORACT Position
| #define SCB_SHCSR_MONITORACT_Pos 8U |
SCB SHCSR: MONITORACT Position
| #define SCB_SHCSR_MONITORACT_Pos 8U |
SCB SHCSR: MONITORACT Position
| #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) |
SCB SHCSR: NMIACT Mask
| #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) |
SCB SHCSR: NMIACT Mask
| #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) |
SCB SHCSR: NMIACT Mask
| #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) |
SCB SHCSR: NMIACT Mask
| #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) |
SCB SHCSR: NMIACT Mask
| #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) |
SCB SHCSR: NMIACT Mask
| #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) |
SCB SHCSR: NMIACT Mask
| #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) |
SCB SHCSR: NMIACT Mask
| #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) |
SCB SHCSR: NMIACT Mask
| #define SCB_SHCSR_NMIACT_Pos 5U |
SCB SHCSR: NMIACT Position
| #define SCB_SHCSR_NMIACT_Pos 5U |
SCB SHCSR: NMIACT Position
| #define SCB_SHCSR_NMIACT_Pos 5U |
SCB SHCSR: NMIACT Position
| #define SCB_SHCSR_NMIACT_Pos 5U |
SCB SHCSR: NMIACT Position
| #define SCB_SHCSR_NMIACT_Pos 5U |
SCB SHCSR: NMIACT Position
| #define SCB_SHCSR_NMIACT_Pos 5U |
SCB SHCSR: NMIACT Position
| #define SCB_SHCSR_NMIACT_Pos 5U |
SCB SHCSR: NMIACT Position
| #define SCB_SHCSR_NMIACT_Pos 5U |
SCB SHCSR: NMIACT Position
| #define SCB_SHCSR_NMIACT_Pos 5U |
SCB SHCSR: NMIACT Position
| #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
SCB SHCSR: PENDSVACT Mask
| #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
SCB SHCSR: PENDSVACT Mask
| #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
SCB SHCSR: PENDSVACT Mask
| #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
SCB SHCSR: PENDSVACT Mask
| #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
SCB SHCSR: PENDSVACT Mask
| #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
SCB SHCSR: PENDSVACT Mask
| #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
SCB SHCSR: PENDSVACT Mask
| #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
SCB SHCSR: PENDSVACT Mask
| #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
SCB SHCSR: PENDSVACT Mask
| #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
SCB SHCSR: PENDSVACT Mask
| #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
SCB SHCSR: PENDSVACT Mask
| #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
SCB SHCSR: PENDSVACT Mask
| #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
SCB SHCSR: PENDSVACT Mask
| #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
SCB SHCSR: PENDSVACT Mask
| #define SCB_SHCSR_PENDSVACT_Pos 10U |
SCB SHCSR: PENDSVACT Position
| #define SCB_SHCSR_PENDSVACT_Pos 10U |
SCB SHCSR: PENDSVACT Position
| #define SCB_SHCSR_PENDSVACT_Pos 10U |
SCB SHCSR: PENDSVACT Position
| #define SCB_SHCSR_PENDSVACT_Pos 10U |
SCB SHCSR: PENDSVACT Position
| #define SCB_SHCSR_PENDSVACT_Pos 10U |
SCB SHCSR: PENDSVACT Position
| #define SCB_SHCSR_PENDSVACT_Pos 10U |
SCB SHCSR: PENDSVACT Position
| #define SCB_SHCSR_PENDSVACT_Pos 10U |
SCB SHCSR: PENDSVACT Position
| #define SCB_SHCSR_PENDSVACT_Pos 10U |
SCB SHCSR: PENDSVACT Position
| #define SCB_SHCSR_PENDSVACT_Pos 10U |
SCB SHCSR: PENDSVACT Position
| #define SCB_SHCSR_PENDSVACT_Pos 10U |
SCB SHCSR: PENDSVACT Position
| #define SCB_SHCSR_PENDSVACT_Pos 10U |
SCB SHCSR: PENDSVACT Position
| #define SCB_SHCSR_PENDSVACT_Pos 10U |
SCB SHCSR: PENDSVACT Position
| #define SCB_SHCSR_PENDSVACT_Pos 10U |
SCB SHCSR: PENDSVACT Position
| #define SCB_SHCSR_PENDSVACT_Pos 10U |
SCB SHCSR: PENDSVACT Position
| #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) |
SCB SHCSR: SECUREFAULTACT Mask
| #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) |
SCB SHCSR: SECUREFAULTACT Mask
| #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) |
SCB SHCSR: SECUREFAULTACT Mask
| #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) |
SCB SHCSR: SECUREFAULTACT Mask
| #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) |
SCB SHCSR: SECUREFAULTACT Mask
| #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) |
SCB SHCSR: SECUREFAULTACT Mask
| #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) |
SCB SHCSR: SECUREFAULTACT Mask
| #define SCB_SHCSR_SECUREFAULTACT_Pos 4U |
SCB SHCSR: SECUREFAULTACT Position
| #define SCB_SHCSR_SECUREFAULTACT_Pos 4U |
SCB SHCSR: SECUREFAULTACT Position
| #define SCB_SHCSR_SECUREFAULTACT_Pos 4U |
SCB SHCSR: SECUREFAULTACT Position
| #define SCB_SHCSR_SECUREFAULTACT_Pos 4U |
SCB SHCSR: SECUREFAULTACT Position
| #define SCB_SHCSR_SECUREFAULTACT_Pos 4U |
SCB SHCSR: SECUREFAULTACT Position
| #define SCB_SHCSR_SECUREFAULTACT_Pos 4U |
SCB SHCSR: SECUREFAULTACT Position
| #define SCB_SHCSR_SECUREFAULTACT_Pos 4U |
SCB SHCSR: SECUREFAULTACT Position
| #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) |
SCB SHCSR: SECUREFAULTENA Mask
| #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) |
SCB SHCSR: SECUREFAULTENA Mask
| #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) |
SCB SHCSR: SECUREFAULTENA Mask
| #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) |
SCB SHCSR: SECUREFAULTENA Mask
| #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) |
SCB SHCSR: SECUREFAULTENA Mask
| #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) |
SCB SHCSR: SECUREFAULTENA Mask
| #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) |
SCB SHCSR: SECUREFAULTENA Mask
| #define SCB_SHCSR_SECUREFAULTENA_Pos 19U |
SCB SHCSR: SECUREFAULTENA Position
| #define SCB_SHCSR_SECUREFAULTENA_Pos 19U |
SCB SHCSR: SECUREFAULTENA Position
| #define SCB_SHCSR_SECUREFAULTENA_Pos 19U |
SCB SHCSR: SECUREFAULTENA Position
| #define SCB_SHCSR_SECUREFAULTENA_Pos 19U |
SCB SHCSR: SECUREFAULTENA Position
| #define SCB_SHCSR_SECUREFAULTENA_Pos 19U |
SCB SHCSR: SECUREFAULTENA Position
| #define SCB_SHCSR_SECUREFAULTENA_Pos 19U |
SCB SHCSR: SECUREFAULTENA Position
| #define SCB_SHCSR_SECUREFAULTENA_Pos 19U |
SCB SHCSR: SECUREFAULTENA Position
| #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) |
SCB SHCSR: SECUREFAULTPENDED Mask
| #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) |
SCB SHCSR: SECUREFAULTPENDED Mask
| #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) |
SCB SHCSR: SECUREFAULTPENDED Mask
| #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) |
SCB SHCSR: SECUREFAULTPENDED Mask
| #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) |
SCB SHCSR: SECUREFAULTPENDED Mask
| #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) |
SCB SHCSR: SECUREFAULTPENDED Mask
| #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) |
SCB SHCSR: SECUREFAULTPENDED Mask
| #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U |
SCB SHCSR: SECUREFAULTPENDED Position
| #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U |
SCB SHCSR: SECUREFAULTPENDED Position
| #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U |
SCB SHCSR: SECUREFAULTPENDED Position
| #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U |
SCB SHCSR: SECUREFAULTPENDED Position
| #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U |
SCB SHCSR: SECUREFAULTPENDED Position
| #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U |
SCB SHCSR: SECUREFAULTPENDED Position
| #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U |
SCB SHCSR: SECUREFAULTPENDED Position
| #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
SCB SHCSR: SVCALLACT Mask
| #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
SCB SHCSR: SVCALLACT Mask
| #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
SCB SHCSR: SVCALLACT Mask
| #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
SCB SHCSR: SVCALLACT Mask
| #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
SCB SHCSR: SVCALLACT Mask
| #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
SCB SHCSR: SVCALLACT Mask
| #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
SCB SHCSR: SVCALLACT Mask
| #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
SCB SHCSR: SVCALLACT Mask
| #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
SCB SHCSR: SVCALLACT Mask
| #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
SCB SHCSR: SVCALLACT Mask
| #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
SCB SHCSR: SVCALLACT Mask
| #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
SCB SHCSR: SVCALLACT Mask
| #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
SCB SHCSR: SVCALLACT Mask
| #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
SCB SHCSR: SVCALLACT Mask
| #define SCB_SHCSR_SVCALLACT_Pos 7U |
SCB SHCSR: SVCALLACT Position
| #define SCB_SHCSR_SVCALLACT_Pos 7U |
SCB SHCSR: SVCALLACT Position
| #define SCB_SHCSR_SVCALLACT_Pos 7U |
SCB SHCSR: SVCALLACT Position
| #define SCB_SHCSR_SVCALLACT_Pos 7U |
SCB SHCSR: SVCALLACT Position
| #define SCB_SHCSR_SVCALLACT_Pos 7U |
SCB SHCSR: SVCALLACT Position
| #define SCB_SHCSR_SVCALLACT_Pos 7U |
SCB SHCSR: SVCALLACT Position
| #define SCB_SHCSR_SVCALLACT_Pos 7U |
SCB SHCSR: SVCALLACT Position
| #define SCB_SHCSR_SVCALLACT_Pos 7U |
SCB SHCSR: SVCALLACT Position
| #define SCB_SHCSR_SVCALLACT_Pos 7U |
SCB SHCSR: SVCALLACT Position
| #define SCB_SHCSR_SVCALLACT_Pos 7U |
SCB SHCSR: SVCALLACT Position
| #define SCB_SHCSR_SVCALLACT_Pos 7U |
SCB SHCSR: SVCALLACT Position
| #define SCB_SHCSR_SVCALLACT_Pos 7U |
SCB SHCSR: SVCALLACT Position
| #define SCB_SHCSR_SVCALLACT_Pos 7U |
SCB SHCSR: SVCALLACT Position
| #define SCB_SHCSR_SVCALLACT_Pos 7U |
SCB SHCSR: SVCALLACT Position
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
| #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
SCB SHCSR: SYSTICKACT Mask
| #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
SCB SHCSR: SYSTICKACT Mask
| #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
SCB SHCSR: SYSTICKACT Mask
| #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
SCB SHCSR: SYSTICKACT Mask
| #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
SCB SHCSR: SYSTICKACT Mask
| #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
SCB SHCSR: SYSTICKACT Mask
| #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
SCB SHCSR: SYSTICKACT Mask
| #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
SCB SHCSR: SYSTICKACT Mask
| #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
SCB SHCSR: SYSTICKACT Mask
| #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
SCB SHCSR: SYSTICKACT Mask
| #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
SCB SHCSR: SYSTICKACT Mask
| #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
SCB SHCSR: SYSTICKACT Mask
| #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
SCB SHCSR: SYSTICKACT Mask
| #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
SCB SHCSR: SYSTICKACT Mask
| #define SCB_SHCSR_SYSTICKACT_Pos 11U |
SCB SHCSR: SYSTICKACT Position
| #define SCB_SHCSR_SYSTICKACT_Pos 11U |
SCB SHCSR: SYSTICKACT Position
| #define SCB_SHCSR_SYSTICKACT_Pos 11U |
SCB SHCSR: SYSTICKACT Position
| #define SCB_SHCSR_SYSTICKACT_Pos 11U |
SCB SHCSR: SYSTICKACT Position
| #define SCB_SHCSR_SYSTICKACT_Pos 11U |
SCB SHCSR: SYSTICKACT Position
| #define SCB_SHCSR_SYSTICKACT_Pos 11U |
SCB SHCSR: SYSTICKACT Position
| #define SCB_SHCSR_SYSTICKACT_Pos 11U |
SCB SHCSR: SYSTICKACT Position
| #define SCB_SHCSR_SYSTICKACT_Pos 11U |
SCB SHCSR: SYSTICKACT Position
| #define SCB_SHCSR_SYSTICKACT_Pos 11U |
SCB SHCSR: SYSTICKACT Position
| #define SCB_SHCSR_SYSTICKACT_Pos 11U |
SCB SHCSR: SYSTICKACT Position
| #define SCB_SHCSR_SYSTICKACT_Pos 11U |
SCB SHCSR: SYSTICKACT Position
| #define SCB_SHCSR_SYSTICKACT_Pos 11U |
SCB SHCSR: SYSTICKACT Position
| #define SCB_SHCSR_SYSTICKACT_Pos 11U |
SCB SHCSR: SYSTICKACT Position
| #define SCB_SHCSR_SYSTICKACT_Pos 11U |
SCB SHCSR: SYSTICKACT Position
| #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
SCB SHCSR: USGFAULTACT Mask
| #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
SCB SHCSR: USGFAULTACT Mask
| #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
SCB SHCSR: USGFAULTACT Mask
| #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
SCB SHCSR: USGFAULTACT Mask
| #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
SCB SHCSR: USGFAULTACT Mask
| #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
SCB SHCSR: USGFAULTACT Mask
| #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
SCB SHCSR: USGFAULTACT Mask
| #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
SCB SHCSR: USGFAULTACT Mask
| #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
SCB SHCSR: USGFAULTACT Mask
| #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
SCB SHCSR: USGFAULTACT Mask
| #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
SCB SHCSR: USGFAULTACT Mask
| #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
SCB SHCSR: USGFAULTACT Mask
| #define SCB_SHCSR_USGFAULTACT_Pos 3U |
SCB SHCSR: USGFAULTACT Position
| #define SCB_SHCSR_USGFAULTACT_Pos 3U |
SCB SHCSR: USGFAULTACT Position
| #define SCB_SHCSR_USGFAULTACT_Pos 3U |
SCB SHCSR: USGFAULTACT Position
| #define SCB_SHCSR_USGFAULTACT_Pos 3U |
SCB SHCSR: USGFAULTACT Position
| #define SCB_SHCSR_USGFAULTACT_Pos 3U |
SCB SHCSR: USGFAULTACT Position
| #define SCB_SHCSR_USGFAULTACT_Pos 3U |
SCB SHCSR: USGFAULTACT Position
| #define SCB_SHCSR_USGFAULTACT_Pos 3U |
SCB SHCSR: USGFAULTACT Position
| #define SCB_SHCSR_USGFAULTACT_Pos 3U |
SCB SHCSR: USGFAULTACT Position
| #define SCB_SHCSR_USGFAULTACT_Pos 3U |
SCB SHCSR: USGFAULTACT Position
| #define SCB_SHCSR_USGFAULTACT_Pos 3U |
SCB SHCSR: USGFAULTACT Position
| #define SCB_SHCSR_USGFAULTACT_Pos 3U |
SCB SHCSR: USGFAULTACT Position
| #define SCB_SHCSR_USGFAULTACT_Pos 3U |
SCB SHCSR: USGFAULTACT Position
| #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
SCB SHCSR: USGFAULTENA Mask
| #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
SCB SHCSR: USGFAULTENA Mask
| #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
SCB SHCSR: USGFAULTENA Mask
| #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
SCB SHCSR: USGFAULTENA Mask
| #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
SCB SHCSR: USGFAULTENA Mask
| #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
SCB SHCSR: USGFAULTENA Mask
| #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
SCB SHCSR: USGFAULTENA Mask
| #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
SCB SHCSR: USGFAULTENA Mask
| #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
SCB SHCSR: USGFAULTENA Mask
| #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
SCB SHCSR: USGFAULTENA Mask
| #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
SCB SHCSR: USGFAULTENA Mask
| #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
SCB SHCSR: USGFAULTENA Mask
| #define SCB_SHCSR_USGFAULTENA_Pos 18U |
SCB SHCSR: USGFAULTENA Position
| #define SCB_SHCSR_USGFAULTENA_Pos 18U |
SCB SHCSR: USGFAULTENA Position
| #define SCB_SHCSR_USGFAULTENA_Pos 18U |
SCB SHCSR: USGFAULTENA Position
| #define SCB_SHCSR_USGFAULTENA_Pos 18U |
SCB SHCSR: USGFAULTENA Position
| #define SCB_SHCSR_USGFAULTENA_Pos 18U |
SCB SHCSR: USGFAULTENA Position
| #define SCB_SHCSR_USGFAULTENA_Pos 18U |
SCB SHCSR: USGFAULTENA Position
| #define SCB_SHCSR_USGFAULTENA_Pos 18U |
SCB SHCSR: USGFAULTENA Position
| #define SCB_SHCSR_USGFAULTENA_Pos 18U |
SCB SHCSR: USGFAULTENA Position
| #define SCB_SHCSR_USGFAULTENA_Pos 18U |
SCB SHCSR: USGFAULTENA Position
| #define SCB_SHCSR_USGFAULTENA_Pos 18U |
SCB SHCSR: USGFAULTENA Position
| #define SCB_SHCSR_USGFAULTENA_Pos 18U |
SCB SHCSR: USGFAULTENA Position
| #define SCB_SHCSR_USGFAULTENA_Pos 18U |
SCB SHCSR: USGFAULTENA Position
| #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
SCB SHCSR: USGFAULTPENDED Mask
| #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
SCB SHCSR: USGFAULTPENDED Mask
| #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
SCB SHCSR: USGFAULTPENDED Mask
| #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
SCB SHCSR: USGFAULTPENDED Mask
| #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
SCB SHCSR: USGFAULTPENDED Mask
| #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
SCB SHCSR: USGFAULTPENDED Mask
| #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
SCB SHCSR: USGFAULTPENDED Mask
| #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
SCB SHCSR: USGFAULTPENDED Mask
| #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
SCB SHCSR: USGFAULTPENDED Mask
| #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
SCB SHCSR: USGFAULTPENDED Mask
| #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
SCB SHCSR: USGFAULTPENDED Mask
| #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
SCB SHCSR: USGFAULTPENDED Mask
| #define SCB_SHCSR_USGFAULTPENDED_Pos 12U |
SCB SHCSR: USGFAULTPENDED Position
| #define SCB_SHCSR_USGFAULTPENDED_Pos 12U |
SCB SHCSR: USGFAULTPENDED Position
| #define SCB_SHCSR_USGFAULTPENDED_Pos 12U |
SCB SHCSR: USGFAULTPENDED Position
| #define SCB_SHCSR_USGFAULTPENDED_Pos 12U |
SCB SHCSR: USGFAULTPENDED Position
| #define SCB_SHCSR_USGFAULTPENDED_Pos 12U |
SCB SHCSR: USGFAULTPENDED Position
| #define SCB_SHCSR_USGFAULTPENDED_Pos 12U |
SCB SHCSR: USGFAULTPENDED Position
| #define SCB_SHCSR_USGFAULTPENDED_Pos 12U |
SCB SHCSR: USGFAULTPENDED Position
| #define SCB_SHCSR_USGFAULTPENDED_Pos 12U |
SCB SHCSR: USGFAULTPENDED Position
| #define SCB_SHCSR_USGFAULTPENDED_Pos 12U |
SCB SHCSR: USGFAULTPENDED Position
| #define SCB_SHCSR_USGFAULTPENDED_Pos 12U |
SCB SHCSR: USGFAULTPENDED Position
| #define SCB_SHCSR_USGFAULTPENDED_Pos 12U |
SCB SHCSR: USGFAULTPENDED Position
| #define SCB_SHCSR_USGFAULTPENDED_Pos 12U |
SCB SHCSR: USGFAULTPENDED Position
| #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) |
SCB STIR: INTID Mask
| #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) |
SCB STIR: INTID Mask
| #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) |
SCB STIR: INTID Mask
| #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) |
SCB STIR: INTID Mask
| #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) |
SCB STIR: INTID Mask
| #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) |
SCB STIR: INTID Mask
| #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) |
SCB STIR: INTID Mask
| #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) |
SCB STIR: INTID Mask
| #define SCB_STIR_INTID_Pos 0U |
SCB STIR: INTID Position
| #define SCB_STIR_INTID_Pos 0U |
SCB STIR: INTID Position
| #define SCB_STIR_INTID_Pos 0U |
SCB STIR: INTID Position
| #define SCB_STIR_INTID_Pos 0U |
SCB STIR: INTID Position
| #define SCB_STIR_INTID_Pos 0U |
SCB STIR: INTID Position
| #define SCB_STIR_INTID_Pos 0U |
SCB STIR: INTID Position
| #define SCB_STIR_INTID_Pos 0U |
SCB STIR: INTID Position
| #define SCB_STIR_INTID_Pos 0U |
SCB STIR: INTID Position
| #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) |
SCB VTOR: TBLBASE Mask
| #define SCB_VTOR_TBLBASE_Pos 29U |
SCB VTOR: TBLBASE Position
| #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
SCB VTOR: TBLOFF Mask
| #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
SCB VTOR: TBLOFF Mask
| #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
SCB VTOR: TBLOFF Mask
| #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
SCB VTOR: TBLOFF Mask
| #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
SCB VTOR: TBLOFF Mask
| #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
SCB VTOR: TBLOFF Mask
| #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
SCB VTOR: TBLOFF Mask
| #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
SCB VTOR: TBLOFF Mask
| #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
SCB VTOR: TBLOFF Mask
| #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
SCB VTOR: TBLOFF Mask
| #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) |
SCB VTOR: TBLOFF Mask
| #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
SCB VTOR: TBLOFF Mask
| #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
SCB VTOR: TBLOFF Mask
| #define SCB_VTOR_TBLOFF_Pos 7U |
SCB VTOR: TBLOFF Position
| #define SCB_VTOR_TBLOFF_Pos 7U |
SCB VTOR: TBLOFF Position
| #define SCB_VTOR_TBLOFF_Pos 7U |
SCB VTOR: TBLOFF Position
| #define SCB_VTOR_TBLOFF_Pos 7U |
SCB VTOR: TBLOFF Position
| #define SCB_VTOR_TBLOFF_Pos 7U |
SCB VTOR: TBLOFF Position
| #define SCB_VTOR_TBLOFF_Pos 7U |
SCB VTOR: TBLOFF Position
| #define SCB_VTOR_TBLOFF_Pos 7U |
SCB VTOR: TBLOFF Position
| #define SCB_VTOR_TBLOFF_Pos 7U |
SCB VTOR: TBLOFF Position
| #define SCB_VTOR_TBLOFF_Pos 7U |
SCB VTOR: TBLOFF Position
| #define SCB_VTOR_TBLOFF_Pos 7U |
SCB VTOR: TBLOFF Position
| #define SCB_VTOR_TBLOFF_Pos 7U |
SCB VTOR: TBLOFF Position
| #define SCB_VTOR_TBLOFF_Pos 7U |
SCB VTOR: TBLOFF Position
| #define SCB_VTOR_TBLOFF_Pos 7U |
SCB VTOR: TBLOFF Position
| #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) |
TPI ACPR: SWOSCALER Mask
| #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) |
TPI ACPR: SWOSCALER Mask
| #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) |
TPI ACPR: SWOSCALER Mask
| #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) |
TPI ACPR: SWOSCALER Mask
| #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) |
TPI ACPR: SWOSCALER Mask
| #define TPI_ACPR_SWOSCALER_Pos 0U |
TPI ACPR: SWOSCALER Position
| #define TPI_ACPR_SWOSCALER_Pos 0U |
TPI ACPR: SWOSCALER Position
| #define TPI_ACPR_SWOSCALER_Pos 0U |
TPI ACPR: SWOSCALER Position
| #define TPI_ACPR_SWOSCALER_Pos 0U |
TPI ACPR: SWOSCALER Position
| #define TPI_ACPR_SWOSCALER_Pos 0U |
TPI ACPR: SWOSCALER Position
| #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) |
TPI DEVID: FIFO depth Mask
TPI DEVID: FIFOSZ Mask
| #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) |
TPI DEVID: FIFOSZ Mask
TPI DEVID: FIFO depth Mask
| #define TPI_DEVID_FIFOSZ_Pos 6U |
TPI DEVID: FIFO depth Position
TPI DEVID: FIFOSZ Position
| #define TPI_DEVID_FIFOSZ_Pos 6U |
TPI DEVID: FIFOSZ Position
TPI DEVID: FIFO depth Position
| #define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) |
TPI FFCR: EnFmt Mask
| #define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) |
TPI FFCR: EnFmt Mask
| #define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) |
TPI FFCR: EnFmt Mask
| #define TPI_FFCR_EnFmt_Pos 0U |
TPI FFCR: EnFmt Position
| #define TPI_FFCR_EnFmt_Pos 0U |
TPI FFCR: EnFmt Position
| #define TPI_FFCR_EnFmt_Pos 0U |
TPI FFCR: EnFmt Position
| #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) |
TPI FFCR: FOnMan Mask
| #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) |
TPI FFCR: FOnMan Mask
| #define TPI_FFCR_FOnMan_Pos 6U |
TPI FFCR: FOnMan Position
| #define TPI_FFCR_FOnMan_Pos 6U |
TPI FFCR: FOnMan Position
| #define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) |
TPI ITATBCTR0: AFVALID1SS Mask
| #define TPI_ITATBCTR0_AFVALID1S_Pos 1U |
TPI ITATBCTR0: AFVALID1S Position
| #define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) |
TPI ITATBCTR0: AFVALID2SS Mask
| #define TPI_ITATBCTR0_AFVALID2S_Pos 1U |
TPI ITATBCTR0: AFVALID2S Position
| #define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) |
TPI ITATBCTR0: ATREADY1S Mask
| #define TPI_ITATBCTR0_ATREADY1S_Pos 0U |
TPI ITATBCTR0: ATREADY1S Position
| #define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) |
TPI ITATBCTR0: ATREADY2S Mask
| #define TPI_ITATBCTR0_ATREADY2S_Pos 0U |
TPI ITATBCTR0: ATREADY2S Position
| #define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) |
TPI ITATBCTR2: AFVALID1SS Mask
| #define TPI_ITATBCTR2_AFVALID1S_Pos 1U |
TPI ITATBCTR2: AFVALID1S Position
| #define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) |
TPI ITATBCTR2: AFVALID2SS Mask
| #define TPI_ITATBCTR2_AFVALID2S_Pos 1U |
TPI ITATBCTR2: AFVALID2S Position
| #define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) |
TPI ITATBCTR2: ATREADY1S Mask
| #define TPI_ITATBCTR2_ATREADY1S_Pos 0U |
TPI ITATBCTR2: ATREADY1S Position
| #define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) |
TPI ITATBCTR2: ATREADY2S Mask
| #define TPI_ITATBCTR2_ATREADY2S_Pos 0U |
TPI ITATBCTR2: ATREADY2S Position
| #define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) |
TPI ITFTTD0: ATB Interface 1 ATVALID Mask
| #define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U |
TPI ITFTTD0: ATB Interface 1 ATVALID Position
| #define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) |
TPI ITFTTD0: ATB Interface 1 byte countt Mask
| #define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U |
TPI ITFTTD0: ATB Interface 1 byte count Position
| #define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) |
TPI ITFTTD0: ATB Interface 1 data0 Mask
| #define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U |
TPI ITFTTD0: ATB Interface 1 data0 Position
| #define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) |
TPI ITFTTD0: ATB Interface 1 data1 Mask
| #define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U |
TPI ITFTTD0: ATB Interface 1 data1 Position
| #define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) |
TPI ITFTTD0: ATB Interface 1 data2 Mask
| #define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U |
TPI ITFTTD0: ATB Interface 1 data2 Position
| #define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) |
TPI ITFTTD0: ATB Interface 2 ATVALID Mask
| #define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U |
TPI ITFTTD0: ATB Interface 2 ATVALIDPosition
| #define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) |
TPI ITFTTD0: ATB Interface 2 byte count Mask
| #define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U |
TPI ITFTTD0: ATB Interface 2 byte count Position
| #define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) |
TPI ITFTTD1: ATB Interface 1 ATVALID Mask
| #define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U |
TPI ITFTTD1: ATB Interface 1 ATVALID Position
| #define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) |
TPI ITFTTD1: ATB Interface 1 byte countt Mask
| #define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U |
TPI ITFTTD1: ATB Interface 1 byte count Position
| #define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) |
TPI ITFTTD1: ATB Interface 2 ATVALID Mask
| #define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U |
TPI ITFTTD1: ATB Interface 2 ATVALID Position
| #define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) |
TPI ITFTTD1: ATB Interface 2 byte count Mask
| #define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U |
TPI ITFTTD1: ATB Interface 2 byte count Position
| #define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) |
TPI ITFTTD1: ATB Interface 2 data0 Mask
| #define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U |
TPI ITFTTD1: ATB Interface 2 data0 Position
| #define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) |
TPI ITFTTD1: ATB Interface 2 data1 Mask
| #define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U |
TPI ITFTTD1: ATB Interface 2 data1 Position
| #define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) |
TPI ITFTTD1: ATB Interface 2 data2 Mask
| #define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U |
TPI ITFTTD1: ATB Interface 2 data2 Position
| #define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) |
TPI LSR: Not thirty-two bit. Mask
| #define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) |
TPI LSR: Not thirty-two bit. Mask
| #define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) |
TPI LSR: Not thirty-two bit. Mask
| #define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) |
TPI LSR: Not thirty-two bit. Mask
| #define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) |
TPI LSR: Not thirty-two bit. Mask
| #define TPI_LSR_nTT_Pos 1U |
TPI LSR: Not thirty-two bit. Position
| #define TPI_LSR_nTT_Pos 1U |
TPI LSR: Not thirty-two bit. Position
| #define TPI_LSR_nTT_Pos 1U |
TPI LSR: Not thirty-two bit. Position
| #define TPI_LSR_nTT_Pos 1U |
TPI LSR: Not thirty-two bit. Position
| #define TPI_LSR_nTT_Pos 1U |
TPI LSR: Not thirty-two bit. Position
| #define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) |
TPI LSR: Software Lock implemented Mask
| #define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) |
TPI LSR: Software Lock implemented Mask
| #define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) |
TPI LSR: Software Lock implemented Mask
| #define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) |
TPI LSR: Software Lock implemented Mask
| #define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) |
TPI LSR: Software Lock implemented Mask
| #define TPI_LSR_SLI_Pos 0U |
TPI LSR: Software Lock implemented Position
| #define TPI_LSR_SLI_Pos 0U |
TPI LSR: Software Lock implemented Position
| #define TPI_LSR_SLI_Pos 0U |
TPI LSR: Software Lock implemented Position
| #define TPI_LSR_SLI_Pos 0U |
TPI LSR: Software Lock implemented Position
| #define TPI_LSR_SLI_Pos 0U |
TPI LSR: Software Lock implemented Position
| #define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) |
TPI LSR: Software Lock status Mask
| #define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) |
TPI LSR: Software Lock status Mask
| #define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) |
TPI LSR: Software Lock status Mask
| #define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) |
TPI LSR: Software Lock status Mask
| #define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) |
TPI LSR: Software Lock status Mask
| #define TPI_LSR_SLK_Pos 1U |
TPI LSR: Software Lock status Position
| #define TPI_LSR_SLK_Pos 1U |
TPI LSR: Software Lock status Position
| #define TPI_LSR_SLK_Pos 1U |
TPI LSR: Software Lock status Position
| #define TPI_LSR_SLK_Pos 1U |
TPI LSR: Software Lock status Position
| #define TPI_LSR_SLK_Pos 1U |
TPI LSR: Software Lock status Position
| #define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) |
TPI PSCR: TPSCount Mask
| #define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) |
TPI PSCR: TPSCount Mask
| #define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) |
TPI PSCR: TPSCount Mask
| #define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) |
TPI PSCR: TPSCount Mask
| #define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) |
TPI PSCR: TPSCount Mask
| #define TPI_PSCR_PSCount_Pos 0U |
TPI PSCR: PSCount Position
| #define TPI_PSCR_PSCount_Pos 0U |
TPI PSCR: PSCount Position
| #define TPI_PSCR_PSCount_Pos 0U |
TPI PSCR: PSCount Position
| #define TPI_PSCR_PSCount_Pos 0U |
TPI PSCR: PSCount Position
| #define TPI_PSCR_PSCount_Pos 0U |
TPI PSCR: PSCount Position